PIC12F1822-I/SN Microchip Technology, PIC12F1822-I/SN Datasheet - Page 35

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PIC12F1822-I/SN

Manufacturer Part Number
PIC12F1822-I/SN
Description
3.5 KB Flash, 128 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 S
Manufacturer
Microchip Technology
Series
PIC® XLP™ 12Fr
Datasheets

Specifications of PIC12F1822-I/SN

Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
No. Of I/o's
6
Eeprom Memory Size
256Byte
Ram Memory Size
128Byte
Embedded Interface Type
AUSART, EUSART, I2C, SPI
No. Of Pins
8
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
Processor Series
PIC12F
Core
PIC
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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TABLE 3-8:
 2010 Microchip Technology Inc.
200h
201h
202h
203h
204h
205h
206h
207h
208h
209h
20Ah
20Bh
20Ch
20Dh
20Eh
20Fh
210h
211h
212h
213h
214h
215h
216h
217h
218h
219h
21Ah
21Bh
21Ch
21Dh
21Eh
21Fh
Legend:
Note
Address
Bank 4
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
1: These registers can be addressed from any bank.
2: PIC16F/LF1823 only.
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
WPUA
WPUC
SSP1BUF
SSP1ADD
SSP1MSK
SSP1STAT
SSP1CON1
SSP1CON2
SSP1CON3
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Name
Shaded locations are unimplemented, read as ‘0’.
(2)
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
Program Counter (PC) Least Significant Byte
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
Working Register
Unimplemented
Unimplemented
Unimplemented
Synchronous Serial Port Receive Buffer/Transmit Register
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
ACKTIM
WCOL
GCEN
Bit 7
SMP
GIE
Write Buffer for the upper 7 bits of the Program Counter
ACKSTAT
SSPOV
PEIE
PCIE
Bit 6
CKE
PIC12F/LF1822/PIC16F/LF1823
TMR0IE
WPUC5
WPUA5
SSPEN
ACKDT
SCIE
Bit 5
D/A
Preliminary
WPUA4
WPUC4
ACKEN
BOEN
Bit 4
INTE
CKP
TO
ADD<7:0>
MSK<7:0>
P
WPUA3
WPUC3
SDAHT
IOCIE
RCEN
Bit 3
PD
S
BSR<4:0>
TMR0IF
WPUA2
WPUC2
SBCDE
Bit 2
R/W
PEN
Z
SSPM<3:0>
WPUC1
WPUA1
RSEN
AHEN
Bit 1
INTF
DC
UA
WPUA0
WPUC0
DHEN
IOCIF
Bit 0
SEN
BF
C
DS41413B-page 35
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 000x 0000 000u
--11 1111 --11 1111
--11 1111 --11 1111
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
POR, BOR
Value on
Value on all
Resets
other

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