AS6C1008-55PCN ALLIANCE MEMORY, AS6C1008-55PCN Datasheet - Page 6
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AS6C1008-55PCN
Manufacturer Part Number
AS6C1008-55PCN
Description
SRAM, 1MB, 2.7V-5.5V, 128KX8, PDIP32
Manufacturer
ALLIANCE MEMORY
Datasheet
1.AS6C1008-55SIN.pdf
(14 pages)
Specifications of AS6C1008-55PCN
Memory Size
1Mbit
Access Time
55ns
Supply Voltage Range
2.7V To 5.5V
Memory Case Style
DIP
No. Of Pins
32
Operating Temperature Range
0°C To +70°C
Operating Temperature Max
70°C
Operating
RoHS Compliant
Memory Configuration
128K X 8
Rohs Compliant
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AS6C1008-55PCN
Manufacturer:
ATM
Quantity:
5 120
WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)
WRITE CYCLE 2 (CE# and CE2 Controlled) (1,2,5,6)
Notes :
1.WE#, CE# must be high or CE2 must be low during all address transitions.
2.A write occurs during the overlap of a low CE#, high CE2, low WE#.
3.During a WE#controlled write cycle with OE# low, t
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5.If the CE#low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high
6.t
Address
Address
placed on the bus.
impedance state.
OW
WE#
WE#
Dout
Dout
CE#
CE2
CE#
CE2
Din
Din
February 2007
02/February/07, v 1.0
and t
WHZ
are specified with C
t
AS
t
L
AS
= 5pF. Transition is measured ±500mV from steady state.
128K X 8 BIT LOW POWER CMOS SRAM
t
(4)
WHZ
(4)
t
WHZ
WP
t
AW
Alliance Memory Inc.
t
must be greater than t
t
AW
CW
t
WP
t
WP
t
t
t
WC
WC
CW
®
t
t
DW
DW
High-Z
High-Z
WHZ
Data Valid
Data Valid
+ t
DW
to allow the drivers to turn off and data to be
t
WR
t
t
DH
DH
t
T
WR
OW
(4)
Page 6 of 14
AS6C1008