CDB4382A Cirrus Logic Inc, CDB4382A Datasheet - Page 24
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CDB4382A
Manufacturer Part Number
CDB4382A
Description
Eval Bd 114dB 192kHz 8Chn DAC W/DSD Supt
Manufacturer
Cirrus Logic Inc
Specifications of CDB4382A
Number Of Dac's
8
Number Of Bits
24
Outputs And Type
8, Single Ended
Sampling Rate (per Second)
192k
Data Interface
Serial
Dac Type
Voltage
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Utilized Ic / Part
CS4382A
Description/function
Audio D/A
Operating Supply Voltage
5 V
Product
Audio Modules
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
CS4382A
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant, Contains lead / RoHS non-compliant
Other names
598-1524
24
4.4
4.5
4.6
SDINx
SDINx
LRCK
SCLK
LRCK
SCLK
1 0
1 0
Oversampling Modes
The CS4382A operates in one of three oversampling modes based on the input sample rate. Mode selection
is determined by the DSD_EN, M3, and M2 pins in Hardware Mode or the FM bits in Software Mode. Single-
speed mode supports input sample rates up to 50 kHz and uses a 128x oversampling ratio. Double-speed
Mode supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad-speed Mode
supports input sample rates up to 200 kHz and uses an oversampling ratio of 32x.
Interpolation Filter
To accommodate the increasingly complex requirements of digital audio systems, the CS4382A incorpo-
rates selectable interpolation filters for each mode of operation. A “fast” and a “slow” roll-off filter is available
in each of Single, Double, and Quad-Speed modes. These filters have been designed to accommodate a
variety of musical tastes and styles. The FILT_SEL bit is used to select which filter is used (see the
Plots” on page 42
When in Hardware Mode, only the “fast” roll-off filter is available.
Filter specifications can be found in
De-emphasis
The CS4382A includes on-chip digital de-emphasis filters. The de-emphasis feature is included to accom-
modate older audio recordings that utilize pre-emphasis equalization as a means of noise reduction.
Figure 13
portionally with changes in sample rate (Fs) if the input sample rate does not match the coefficient which
has been selected.
19 18
shows the de-emphasis curve. The frequency response of the de-emphasis curve will scale pro-
17 16
17 16
15 14 13 12 11 10
15 14 13 12 11 10
for more details).
Left Channel
32 clocks
Left Channel
32 clocks
Figure 12. Format 5 - Right-Justified 18-bit Data
Figure 11. Format 4 - Right-Justified 20-bit Data
9 8 7
9 8 7
Section
6 5 4 3 2 1 0
6 5 4 3 2 1 0
2, and filter response plots can be found in
19 18
17 16
17 16
15 14 13 12 11 10
15 14 13 12 11 10
Right Channel
Right Channel
9 8 7
9 8 7
6 5 4 3 2 1 0
6 5 4 3 2 1 0
Figures 20
CS4382A
DS618F2
to 43.
“Filter