CS4334-KS Cirrus Logic Inc, CS4334-KS Datasheet - Page 12

• Manufacturer Part Number: CS4334-KS
• Description: D/A Converter (D-A) IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS4334-KS

• No. Of Pins: 8
• Peak Reflow Compatible (260 C): No
• Supply Voltage Max: 5V
• No. Of Bits: 24 Bit
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Interface Type: Serial
• Package / Case: 8-SOIC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

4. SYSTEM DESIGN
The CS4334 family accepts data at standard audio
sample rates including 48, 44.1 and 32 kHz in
BRM and 96, 88.2 and 64 kHz in HRM. Audio data
is input via the serial data input pin (SDATA). The
Left/Right Clock (LRCK) defines the channel and
delineation of data, and the Serial Clock (SCLK)
clocks audio data into the input data buffer. The
CS4334/5/6/7/8/9 differ in serial data formats as
shown in Figures 10-15.
4.1 Master Clock
MCLK must be either 256x, 384x or 512x the de-
sired input sample rate in BRM and either 128x or
192x the desired input sample rate in HRM. The
LRCK frequency is equal to Fs, the frequency at
which words for each channel are input to the de-
vice. The MCLK-to-LRCK frequency ratio is de-
tected automatically during the initialization
sequence by counting the number of MCLK transi-
tions during a single LRCK period. Internal divid-
ers are set to generate the proper clocks. Table 1
illustrates several standard audio sample rates and
the required MCLK and LRCK frequencies. Please
note there is no required phase relationship, but
MCLK, LRCK and SCLK must be synchronous.
4.2 Serial Clock
The serial clock controls the shifting of data into
the input data buffers. The CS4334 family supports
both external and internal serial clock generation
modes. Refer to Figures 10-15 for data formats.
12
LRCK
(kHz)
44.1
88.2
32
48
64
96
11.2896 16.9344
12.2880 18.4320
Table 1. Common Clock Frequencies
4.0960
5.6448
6.1440
8.1920 12.2880
128x
HRM
6.1440
8.4672 11.2896 16.9344 22.5792
9.2160 12.2880 18.4320 24.5760
192x
MCLK (MHz)
8.1920 12.2880 16.3840
256x
-
-
-
BRM
384x
-
-
-
512x
-
-
-
4.2.1 External Serial Clock Mode
The CS4334 family will enter the External Serial
Clock Mode when 16 low to high transitions are
detected on the DEM/SCLK pin during any phase
of the LRCK period. When this mode is enabled,
the Internal Serial Clock Mode and de-emphasis
filter cannot be accessed. The CS4334 family will
switch to Internal Serial Clock Mode if no low to
high transitions are detected on the DEM/SCLK
pin for 2 consecutive frames of LRCK. Refer to
Figure 16.
4.2.2 Internal Serial Clock Mode
In the Internal Serial Clock Mode, the serial clock
is internally derived and synchronous with MCLK
and LRCK. The SCLK/LRCK frequency ratio is ei-
ther 32, 48, or 64 depending upon data format. Op-
eration in this mode is identical to operation with
an external serial clock synchronized with LRCK.
This mode allows access to the digital de-emphasis
function. Refer to Figures 10 - 16 for details.
While the Internal Serial Clock Mode is provided
to allow access to the de-emphasis filter, the Inter-
nal Serial Clock Mode also eliminates possible
clock interference from an external SCLK.
4.3 De-Emphasis
The CS4334 family includes on-chip digital de-em-
phasis. Figure 9 shows the de-emphasis curve for
Fs equal to 44.1 kHz. The frequency response of
the de-emphasis curve will scale proportionally
with changes in sample rate, Fs.
The de-emphasis filter is active (inactive) if the
DEM/SCLK pin is low (high) for 5 consecutive
falling edges of LRCK. This function is available
only in the internal serial clock mode.
4.4 Initialization and Power-Down
The Initialization and Power-Down sequence flow
chart is shown in Figure 16. The CS4334 family en-
ters the Power-Down State upon initial power-up.
CS4334/5/6/7/8/9
DS248PP3