CS4334-DSZ Cirrus Logic Inc, CS4334-DSZ Datasheet
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CS4334-DSZ
Specifications of CS4334-DSZ
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CS4334-DSZ Summary of contents
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... Confidential Draft 3/11/08 Description The CS4334 family members are complete, stereo dig- ital-to-analog output systems including interpolation, 1-bit D/A conversion and output analog filtering in an 8-pin package. The CS4334/5/8/9 support all major au- dio data interface formats, and the individual devices differ only in the supported interface format ...
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... System Block Diagram............................................................................................................. 12 Figure 9. De-Emphasis Curve (Fs = 44.1kHz) ........................................................................................ 14 Figure 10. CS4334 Data Format (I²S) ....................................................................................................... 15 Figure 11. CS4335 Data Format ............................................................................................................... 15 Figure 12. CS4338 Data Format ............................................................................................................... 16 Figure 13. CS4339 Data Format ............................................................................................................... 16 Figure 14. CS4334/5/8/9 Initialization and Power-Down Sequence ......................................................... 17 Figure 15. Stopband Rejection.................................................................................................................. 18 Figure 16. Transition Band........................................................................................................................ 18 Figure 17. Transition Band........................................................................................................................ 18 2 Confidential Draft 3/11/08 ...
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... Serial Audio Data Input - Two’s complement MSB-first serial data is input on this pin. The data is 1 SDATA I clocked into the CS4334/5/8/9 via internal or external SCLK, and the channel is determined by LRCK. De-Emphasis/External Serial Clock Input - Used for de-emphasis filter control or external serial 2 ...
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... Figure 1. Recommended Connection Diagram 4 Confidential Draft 3/11/08 + 0.1 µF 1 µ 3.3 µF 8 AOUTL + Ω 267 CS4334 CS4335 CS4338 CS4339 3.3 µF 5 AOUTR + Ω 267 CS4334/5/8/9 +5V Ω 560 Left Audio Output Ω Ω 560 Right Audio Output Ω 560 π 4 Fs(R 560) L DS248F5 ...
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... WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. DS248F5 Confidential Draft 3/11/08 Symbol Min VA 4.75 -KSZ T -10 A -DSZ -40 Symbol IND stg CS4334/5/8/9 Nom Max Units 5.0 5.5 V °C - +70 °C - +85 Min Max Units -0.3 6 ±10 mA -0.3 VA+0.4 V ...
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... ANALOG CHARACTERISTICS (Full-Scale Output Sine Wave, 997 Hz; Test load R 48 kHz, Measurement Bandwidth kHz, unless otherwise specified; Fs for High-Rate Mode = 96 kHz, Measurement Bandwidth kHz, unless otherwise specified.) Parameter Dynamic Performance for CS4334/5/8/9-KSZ Dynamic Range 18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise ...
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... Base-Rate Mode Symbol Min Typ (Note 2) (Note -. .5465 - (Note tgd - 9/ kHz - ±0.36/ kHz kHz - - - - kHz - - Symbol V Q (Note (Note CS4334/5/8/9 High-Rate Mode Max Min Typ Max Unit .4780 - - - - 0 - .4650 .4996 0 - .4982 +.08 -.05 - +.2 ±. ±.2 - .5770 - - - 4/ ±1.39/ ±0.23/Fs - +1.5/+0 +.05/-.25 (Note 5) - ...
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... Figure 4. Max Power Dissipation is measured at VA=5.5V. AGND 8 Confidential Draft 3/11/08 Symbol Min normal operation I A power-down state I A (Note 7) normal operation power-down θ kHz) PSRR 10 µF AOUTx R L Figure 2. Output Test Load CS4334/5/8/9 Typ Max Units - µ 104 110 - °C/Watt - 79 ...
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... High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Input Capacitance Notes for CS433X LRCK is ±20µA max. in DS248F5 Confidential Draft 3/11/ Ω Figure 4. Power vs. Sample Rate Symbol (Note CS4334/5/8 Sample Rate (kHz) Min Typ Max Units 2 0 ± 100 V V µ ...
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... Confidential Draft 3/11/08 Symbol Fs MCLK/LRCK = 512 MCLK/LRCK = 512 t sclkl t sclkh Base-Rate Mode t sclkw High-Rate Mode t sclkw t slrd t slrs t sdlrs t sdh (Note 9) t sclkw (Note 10) t sclkr t sdlrs t sdh t sdh --------------------- - ( 10-13) CS4334/5/8/9 Min Typ Max 2 - 100 10 - 1000 10 - 1000 21 - 1000 21 - 1000 31 - 1000 31 - 1000 --------------------- - ( ...
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... Figure 5. External Serial Mode Input Timing * Figure 6. Internal Serial Mode Input Timing The SCLK pulses shown are internal to the CS4334/5/8/9. LRCK MCLK *INTERNAL SCLK SDATA Figure 7. Internal Serial Clock Generation * The SCLK pulses shown are internal to the CS4334/5/8/9. DS248F5 Confidential Draft 3/11/ sclkh slrs t slrd t ...
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... The CS4334 family of devices supports two modes of operation. The devices operate in Base Rate Mode (BRM) when MCLK/LRCK is 256, 384 or 512 and in High Rate Mode (HRM) when MCLK/LRCK is 128 or 192. High Rate Mode allows input sample rates up to 100 kHz ...
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... SYSTEM DESIGN The CS4334 family accepts data at standard audio sample rates including 48, 44.1 and 32 kHz in BRM and 96, 88.2 and 64 kHz in HRM. Audio data is input via the serial data input pin (SDATA). The Left/Right Clock (LRCK) defines the channel and delineation of data, and the Serial Clock (SCLK) clocks audio data into the input data buffer. The CS4334/5/8/9 differ in serial data formats as shown in 4 ...
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... Q 4.5 Output Transient Control The CS4334 family uses Popguard® technology to minimize the effects of output transients during power- up and power-down. This technique eliminates the audio transients commonly produced by single-ended single-supply converters when it is implemented with external DC-blocking capacitors connected in series with the audio outputs. To make best use of this feature necessary to understand its operation. ...
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... Analog Output and Filtering The analog filter present in the CS4334 family is a switched-capacitor filter followed by a continuous time low pass filter. Its response, combined with that of the digital interpolator, is given nel ...
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... Data Valid on Rising Edge of SCLK SCLK Must Have at Least 32 Cycles per LRCK Period Figure 12. CS4338 Data Format Right Justified, 18-Bit Data Data Valid on Rising Edge of SCLK SCLK Must Have at Least 36 Cycles per LRCK Period Figure 13. CS4339 Data Format CS4334/5/8 External SCLK Mode ...
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... Figure 14. CS4334/5/8/9 Initialization and Power-Down Sequence DS248F5 Confidential Draft 3/11/08 CS4334/5/8/9 17 ...
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... Overall Base-Rate Frequency Response Figure 15. Stopband Rejection Figure 17. Transition Band 18 Confidential Draft 3/11/08 Figure 16. Transition Band Figure 18. Passband Ripple CS4334/5/8/9 DS248F5 ...
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... Overall High-Rate Frequency Response Figure 19. Stopband Rejection Figure 21. Transition Band DS248F5 Confidential Draft 3/11/08 Figure 20. Transition Band Figure 22. Passband Ripple CS4334/5/8/9 19 ...
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... Figure 28. THD+N vs. Frequency (BRM) System Two Cascade. CS4334/5/8 10k 12k 14k 16k 10k 10k 12k 12k 14k 14k 16k 16k ...
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... Figure 34. THD+N vs. Frequency (HRM) System Two Cascade. CS4334/5/8 10k 10k 10k 12k 12k 12k 14k 14k 14k 16k 16k 16k 2k ...
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... The change in gain value with temperature. Units in ppm/°C. 6. REFERENCES 1. "How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992. 2. CDB4334/5/8/9 Evaluation Board Datasheet 22 Confidential Draft 3/11/08 CS4334/5/8/9 DS248F5 ...
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... JEDEC # : MS-012 CS4334/5/8/9 ∝ L MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 3.80 4.00 1.02 1.52 5.80 6 ...
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... FUNCTIONAL COMPATIBILITY CS4330-KS ⇒ CS4339-KSZ CS4331-KS ⇒ CS4334-KSZ CS4333-KS ⇒ CS4338-KSZ CS4330-BS ⇒ CS4339-DSZ CS4331-BS ⇒ CS4334-DSZ CS4333-BS ⇒ CS4338-DSZ 10.REVISION HISTORY Revision F3 Removed CS4335-BS and CS4339-BS from the Ordering Information section. Removed CS4334-BS & CS4349-BS and updated all other packages to lead-free. Functional compatibility F4 was updated to reflect that of the new lead-free packages ...