CS4334-DSZ Cirrus Logic Inc, CS4334-DSZ Datasheet - Page 10

• Manufacturer Part Number: CS4334-DSZ
• Description: IC DAC STER 24BIT 96KHZ 8-SOIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS4334-DSZ

• Data Interface: Serial
• Number Of Bits: 24
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 104mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC
• Resolution (bits): 24bit
• Sampling Rate: 96kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 4.75V To 5.5V
• Supply Current: 15mA
• Digital Ic Case Style: SOIC
• Package: 8SOIC
• Resolution: 24 Bit
• Conversion Rate: 96 KSPS
• Architecture: Delta-Sigma
• Digital Interface Type: Serial
• Number Of Outputs Per Chip: 2
• Output Type: Voltage
• Full Scale Error: ±5(Typ) %FSR
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1510 - BOARD EVAL FOR CS4334 CODEC
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1631

10
SWITCHING CHARACTERISTICS
Notes:
Input Sample Rate
MCLK Pulse Width High
MCLK Pulse Width Low
MCLK Pulse Width High
MCLK Pulse Width Low
MCLK Pulse Width High
MCLK Pulse Width Low
External SCLK Mode
LRCK Duty Cycle (External SCLK only)
SCLK Pulse Width Low
SCLK Pulse Width High
SCLK Period
MCLK / LRCK = 512, 256 or 384
SCLK Period
MCLK / LRCK = 128 or 192
SCLK rising to LRCK edge delay
SCLK rising to LRCK edge setup time
SDATA valid to SCLK rising setup time
SCLK rising to SDATA hold time
Internal SCLK Mode
LRCK Duty Cycle (Internal SCLK only)
SCLK Period
SCLK rising to LRCK edge
SDATA valid to SCLK rising setup time
SCLK rising to SDATA hold time
SCLK rising to SDATA hold time
9. In Internal SCLK Mode, the Duty Cycle must be 50% +/− 1/2 MCLK Period.
10. The SCLK / LRCK ratio may be either 32, 48, or 64. This ratio depends on part type and MCLK/LRCK
ratio. (See figures
Parameters
MCLK / LRCK = 512, 256 or 128
MCLK / LRCK = 384 or 192
MCLK / LRCK = 384 or 192
MCLK / LRCK = 384 or 192
MCLK / LRCK = 256 or 128
MCLK / LRCK = 256 or 128
Figures
MCLK/LRCK = 512
MCLK/LRCK = 512
Base-Rate Mode
10-13)
High-Rate Mode
(Note 10)
Confidential Draft
(Note 9)
3/11/08
Symbol
t
t
t
t
t
t
t
t
sclkw
sclkw
sclkw
sclkh
t
t
t
t
t
sdlrs
sdlrs
sclkl
sclkr
Fs
slrd
sdh
sdh
sdh
slrs
--------------------- -
(
--------------------- -
(
--------------------- -
(
384
512
512
1
--------------------- -
(
1
1
---------------- -
SCLK
128
)Fs
------------------ -
(
)Fs
)Fs
Min
64
10
10
21
21
31
31
40
20
20
20
20
20
20
1
1
2
1
-
-
)Fs
)Fs
+
+
+
15
10
15
tsclkw
----------------- -
Typ
50
50
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CS4334/5/8/9
Max
1000
1000
1000
1000
1000
1000
100
60
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DS248F5
Units
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
%
%