CS4954-CQ Cirrus Logic Inc, CS4954-CQ Datasheet - Page 23

• Manufacturer Part Number: CS4954-CQ
• Description: Digital Video Encoder IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS4954-CQ

• No. Of Pins: 48
• Peak Reflow Compatible (260 C): No
• Ic Function: Digital Video Encoder IC
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

H-sync can be delayed by a full line, in 74 nsec in-
tervals.
V-sync can be shifted in both directions in time.
The default values are 18 and 23 for NTSC and
PAL respectively. Since the V-sync register is 5
bits wide (Sync Register 0), the V-sync pulse can
be shifted by 31 lines in total.
V-sync can preceed by a maximum of 18 lines
(NTSC) or 23 lines (PAL) respectively from its de-
fault location, and V-sync can follow by a maxi-
mum of 13 lines (NTSC) or 8 lines (PAL) from its
default location.
5.10. Wide Screen Signaling (WSS) and
Wide screen signaling support is provided for
NTSC and for PAL standards. Wide screen signal-
ing is currently used in most countries with 625 line
systems as well as in Japan for EDTV-II applica-
tions. For complete description of WSS standard,
please refer to ITU-R BT.1119 (625 line system)
and to EIAJ CPX1204 for the Japanese 525 line
system.
The wide screen signal is transferred in a blanking
line of each video field (NTSC: lines 20 and 283,
PAL: lines 23 and 336). Wide screen signaling is
enabled by setting WW_23 to “1”. Some countries
with PAL standard don’t use line 336 for wide
screen signaling (they use only line 23), therefore
we provide another enable bit (WSS_22) for that
particular line.
There are 3 registers dedicated to contain the trans-
mitted WSS bits (WSS_REG_0, WSS_REG_1,
WSS_REG_2). The data insertion into the appro-
priate lines are performed automatically by this de-
vice. The run-in and start code bits do not have to
be loaded into this device, it automatically inserts
the correct code at the beginning of transfer.
DS278PP4
CGMS
5.11. Teletext Support
This chip supports several teletext standards, like
European teletext, NABTS (North American tele-
text), and WST (World Standard Teletext) for
NTSC and PAL.
All these teletext standards are defined in the ITU-
R BT.653-2 document. The European teletext is
defined as “teletext system B” for 625/50 Hz TV
systems. NABTS teletext is defined as “teletext
system C” for 525/60 Hz TV systems. WST for
PAL is defined as “teletext system D” for
624/50 Hz TV systems and WST for NTSC is de-
fined as “teletext system D” for 525/60 Hz TV
systems.
This chip provides independant teletext encoding
into composite 1, composite 2 and s-video signals.
The teletext encoding into these various signals is
software programmable.
In teletext pulsation mode, (TTX_WINDOW=0),
register 0×31 bit 3, the pin TTXDAT receives a
teletext bitstream sampled at the 27 Mhz clock. At
each rising edge of the TTXRQ output signal a sin-
gle teletext bit has to be provided after a program-
mable input delay at the TTXDAT input pin.
Phase variant interpolation is achieved on this bit-
stream in the internal teletext encoder, providing
sufficient small phase jitter on the ouput text lines.
TTXRQ provides a fully programmable request
signal to the teletext source, indicating the insertion
period of the bitstream at indepenantly selectable
lines for both TV fields. The internal insertion win-
dow for text is set to either 360, 296 or 288 teletext
bits, depending on the selected teletext standard.
The clock run-in is included in this window.
Teletext in enabled by setting the TTX_EN bit to
“1”. The TTX_WST bit in conjunction with the
TV_FORMAT register select one of the 4 possible
teletext encoding possibilities.
The teletext timing is shown in the Figure 12.
TTXHS and TTXHD are user programmable and
CS4954 CS4955
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