DSPIC30F2023-20E/ML Microchip Technology, DSPIC30F2023-20E/ML Datasheet - Page 186
DSPIC30F2023-20E/ML
Manufacturer Part Number
DSPIC30F2023-20E/ML
Description
12KB, Flash, 512bytes-RAM, 30MIPS, 35I/O, 16-bit Family,nanoWatt 44 QFN 8x8x0.9m
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.AC164335.pdf
(286 pages)
2.DM300023.pdf
(22 pages)
3.DM300023.pdf
(18 pages)
4.DSPIC30F2011-20ISO.pdf
(66 pages)
5.DSPIC30F2011-20IP.pdf
(26 pages)
6.DSPIC30F1010-30ISO.pdf
(26 pages)
7.DSPIC30F1010-30ISO.pdf
(50 pages)
Specifications of DSPIC30F2023-20E/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
12KB (4K x 24)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F2023-20E/ML
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- AC164335 PDF datasheet
- DM300023 PDF datasheet #2
- DM300023 PDF datasheet #3
- DSPIC30F2011-20ISO PDF datasheet #4
- DSPIC30F2011-20IP PDF datasheet #5
- DSPIC30F1010-30ISO PDF datasheet #6
- DSPIC30F1010-30ISO PDF datasheet #7
- Current page: 186 of 286
- Download datasheet (5Mb)
dsPIC30F1010/202X
Example 16-1 shows a code sequence for using the
ADBASE register to implement ADC Input Pair Inter-
rupt Handling. When the ADBASE register is read, it
contains the sum of the base address of the jump table
and the encoded ADC channel pair number left shifted
by 2 bits.
EXAMPLE 16-1:
DS70178C-page 184
; Initialize and enable the ADC interrupt
; Code to Initialize the rest of the ADC registers
; ADC Interrupt Handler
__ADCInterrupt:
; Here's the Jump Table
; Note: It is important to clear the individual IRQ flags in the ADC AFTER the IRQ flags
in the interrupt controller. Failure to do so may cause interrupt requests to be lost
JMP_TBL:
MOV
MOV WO, ADBASE
BSET
BSET
BSET
BCLR
BCLR
BSET
...
...
...
PUSH.S
BCLR
MOV
GOTO
BCLR
BRA
BCLR
BRA
BCLR
BRA
BCLR
BRA
BCLR
BRA
#handle(JMP_TBL),W0
IPC2,#12
IPC2,#13
IPC2,#14
IFS0,#11
ADSTAT
IEC0,#11
IFSO,#11
ADBASE, W0
W0
ADSTAT,#0
ADC_PAIR0_PROC
ADSTAT,#1
ADC_PAIR1_PROC
ADSTAT,#2
ADC_PAIR2_PROC
ADSTAT,#3
ADC_PAIR3_PROC
ADSTAT,#4
ADC_PAIR4_PROC
ADC BASE REGISTER CODE
; Load the base address of the ISR Jump
; table in ADBASE.
; Set up the interrupt priority
; Clear any pending interrupts
; Clear the ADC pair interrupts as well
; Enable the interrupt
; Save WO-W3 and SR registers
; Clear the interrupt
; ADBASE contains the encoded jump address
; within JMP_TBL
; Clear the IRQ flag in the ADC
; Actual Pair 0 Conversion Interrupt Handler
; Clear the IRQ flag in the ADC
; Actual Pair 1 Conversion Interrupt Handler
; Clear the IRQ flag in the ADC
; Clear the IRQ flag in the ADC
; Actual Pair 3 Conversion Interrupt Handler
; Clear the IRQ flag in the ADC
; Actual Pair 4 Conversion Interrupt Handler
; Actual Pair 2 Conversion Interrupt Handler
Preliminary
For example, if ADBASE is initialized with a value of
0x0360, a channel pair 1 interrupt would cause an
ADBASE
0b00000100). A channel pair 3 interrupt would cause
an ADBASE read value of 0x036C (0x360 +
0b00001100).
read
value
© 2006 Microchip Technology Inc.
of
0x0364
(0x360
+
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