DSPIC30F3011-30I/ML Microchip Technology, DSPIC30F3011-30I/ML Datasheet - Page 108

• Manufacturer Part Number: DSPIC30F3011-30I/ML
• Description: IC,DSP,16-BIT,CMOS,LLCC,44PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3011-30I/ML

• Rohs Compliant: YES
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 24KB (8K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFNDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DSPIC30F301130IML

dsPIC30F3010/3011
16.2
The module supports a basic framed SPI protocol in
Master or Slave mode. The control bit, FRMEN,
enables framed SPI support and causes the SS1 pin to
perform the Frame Synchronization (F
function. The control bit, SPIFSD, determines whether
FIGURE 16-1:
FIGURE 16-2:
DS70141F-page 108
Note: x = 1 or 2, y = 1 or 2.
Framed SPI Support
SDO1
SCK1
SDI1
SS1
MSb
PROCESSOR 1
SPI BLOCK DIAGRAM
SPI MASTER/SLAVE CONNECTION
Serial Input Buffer
SSx & FSYNC
SPI Master
Shift Register
(SPIxBUF)
Control
(SPIxSR)
Receive
Read
SPI1BUF
bit 0
LSb
SPI1SR
SYNC
Control
SDOx
SCKx
Clock
SDIx
) pulse
clock
Shift
SPI1BUF
Write
Transmit
Serial Clock
Data Bus
Internal
Select
Edge
the SS1 pin is an input or an output (i.e., whether the
module receives or generates the frame synchroniza-
tion pulse). The frame pulse is an active-high pulse for
a single SPI clock cycle. When frame synchronization
is enabled, the data transmission starts only on the
subsequent transmit edge of the SPI clock.
SDOy
SCKy
SDIy
Enable Master Clock
MSb
Secondary
Prescaler
1:1 – 1:8
Serial Input Buffer
Shift Register
PROCESSOR 2
(SPIyBUF)
(SPIySR)
SPI Slave
© 2010 Microchip Technology Inc.
1, 4, 16, 64
Prescaler
Primary
LSb
F
CY