DSPIC30F4013-20E/ML Microchip Technology, DSPIC30F4013-20E/ML Datasheet - Page 5
![IC,DSP,16-BIT,CMOS,LLCC,44PIN,PLASTIC](/photos/6/81/68122/150-44-qfn_sml.jpg)
DSPIC30F4013-20E/ML
Manufacturer Part Number
DSPIC30F4013-20E/ML
Description
IC,DSP,16-BIT,CMOS,LLCC,44PIN,PLASTIC
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F3014-30IPT.pdf
(228 pages)
3.DSPIC30F3014-30IPT.pdf
(16 pages)
4.DSPIC30F3014-30IPT.pdf
(6 pages)
5.DSPIC30F3014-30IPT.pdf
(14 pages)
6.DSPIC30F3014-30IPT.pdf
(20 pages)
Specifications of DSPIC30F4013-20E/ML
Rohs Compliant
YES
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
Number Of I /o
30
Program Memory Size
48KB (16K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 13x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
DSPIC30F401320EML
4. Module: Interrupt Controller – Sequential
© 2008 Microchip Technology Inc.
When interrupt nesting is enabled (or NSTDIS
(INTCON1<15>) bit is ‘0’) the following sequence
of events will lead to an address error trap. The
generic terms “Interrupt 1” and “Interrupt 2” are
used to represent any two enabled dsPIC30F
interrupts.
1. Interrupt 1 processing begins.
2. Interrupt 1 is negated by user software by one
3. Interrupt 2 occurs with a priority higher than
EXAMPLE 4: USING DISI
EXAMPLE 5: RAISING CPU INTERRUPT PRIORITY LEVEL
EXAMPLE 6: USING MACRO
.include
...
DISI#2 ; protect the disable of INT1
BCLRIEC1, #INT1IE; disable interrupt 1
...
.include
...
__asm__ volatile (“DISI #0x1FFF”);
SRbits.IPL = 0x5;
DISICNT = 0x0;
#define DISI_PROTECT(X) {\
DISI_PROTECT(SRbits.IPL = 0x5);
of the following methods:
- CPU IPL is raised to Interrupt 1 IPL level or
- Interrupt 1 IPL is lowered to CPU IPL level or
- Interrupt 1 is disabled (Interrupt 1 IE bit set to
- Interrupt 1 flag is cleared
Interrupt 1.
higher or
lower or
‘0’) or
__asm__ volatile (“DISI #0x1FFF”);\
X;
DISICNT = 0; }
; next instruction protected by DISI
Interrupts
“p30fxxxx.inc”
“p30fxxxx.h”
\
// safely modify the CPU IPL
// protect CPU IPL modification
// set CPU IPL to 5
// remove DISI protection
dsPIC30F3014/4013
Work around
The user may disable interrupt nesting or execute
a DISI instruction before modifying the CPU IPL
or Interrupt 1 setting. A minimum DISI value of 2
is required if the DISI is executed immediately
before the CPU IPL or Interrupt 1 is modified, as
shown in Example 4. If the MPLAB C30 compiler
is being used, one must inspect the Disassembly
Listing in the MPLAB IDE file to determine the
exact number of cycles to disable level 1-6
interrupts. One may use a large DISI value and
then set the DISICNT register to zero, as shown in
Example 5. A macro may also be used to perform
this task, as shown in Example 6.
DS80397A-page 5