DSPIC30F4013-20E/P Microchip Technology, DSPIC30F4013-20E/P Datasheet - Page 30
![IC,DSP,16-BIT,CMOS,DIP,40PIN,PLASTIC](/photos/6/61/66192/150-40-dip_sml.jpg)
DSPIC30F4013-20E/P
Manufacturer Part Number
DSPIC30F4013-20E/P
Description
IC,DSP,16-BIT,CMOS,DIP,40PIN,PLASTIC
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20IP.pdf
(26 pages)
3.DSPIC30F3014-30IPT.pdf
(228 pages)
4.DSPIC30F3014-30IPT.pdf
(16 pages)
5.DSPIC30F3014-30IPT.pdf
(6 pages)
6.DSPIC30F3014-30IPT.pdf
(14 pages)
7.DSPIC30F3014-30IPT.pdf
(20 pages)
Specifications of DSPIC30F4013-20E/P
Rohs Compliant
YES
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
Number Of I /o
30
Program Memory Size
48KB (16K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 13x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
AC30F003 - MODULE SOCKET DSPIC30F 40DIPACICE0206 - ADAPTER MPLABICE 40P 600 MIL
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
DSPIC30F4013-20EP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F4013-20E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- DSPIC30F2011-20ISO PDF datasheet
- DSPIC30F2011-20IP PDF datasheet #2
- DSPIC30F3014-30IPT PDF datasheet #3
- DSPIC30F3014-30IPT PDF datasheet #4
- DSPIC30F3014-30IPT PDF datasheet #5
- DSPIC30F3014-30IPT PDF datasheet #6
- DSPIC30F3014-30IPT PDF datasheet #7
- Current page: 30 of 228
- Download datasheet (2Mb)
dsPIC30F3014/4013
3.2
The core has two data spaces. The data spaces can be
considered either separate (for some DSP instructions),
or as one unified linear address range (for MCU instruc-
tions). The data spaces are accessed using two Address
Generation Units (AGUs) and separate data paths.
3.2.1
The data space memory is split into two blocks, X and
Y data space. A key element of this architecture is that
Y space is a subset of X space, and is fully contained
within X space. In order to provide an apparent Linear
Addressing space, X and Y spaces have contiguous
addresses.
FIGURE 3-7:
DS70138G-page 30
Data Address Space
Optionally
Mapped
into Program
Memory
DATA SPACE MEMORY MAP
SRAM Space
2 Kbyte
SFR Space
2 Kbyte
dsPIC30F3014/dsPIC30F4013 DATA SPACE MEMORY MAP
Address
MSB
0x1FFF
0x0001
0x07FF
0x0801
0x0BFF
0x0C01
0x0FFF
0x1001
0x8001
0xFFFF
MSB
Unimplemented (X)
Y Data RAM (Y)
X Data RAM (X)
16 bits
SFR Space
X Data
When executing any instruction other than one of
the MAC class of instructions, the X block consists of the
64-Kbyte data address space (including all Y addresses).
When executing one of the MAC class of instructions, the
X block consists of the 64-Kbyte data address space
excluding the Y address block (for data reads only). In
other words, all other instructions regard the entire data
memory as one composite address space. The MAC
class instructions extract the Y address space from data
space and address it using EAs sourced from W10 and
W11. The remaining X data space is addressed using W8
and W9. Both address spaces are concurrently accessed
only with the MAC class instructions.
The data space memory map is shown in
LSB
0x0000
0x07FE
0x0800
0x0BFE
0x0C00
0x0FFE
0x1000
0x1FFE
0x8000
0xFFFE
Address
LSB
2010 Microchip Technology Inc.
8 Kbyte
Near
Data
Space
Figure
3-7.
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