HSP50214BVC Intersil, HSP50214BVC Datasheet - Page 28
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HSP50214BVC
Manufacturer Part Number
HSP50214BVC
Description
IC's, Microprocessor Support
Manufacturer
Intersil
Datasheet
1.HSP50214BVC.pdf
(62 pages)
Specifications of HSP50214BVC
No. Of Pins
120
Mounting Type
Surface Mount
No. Of Channels
1
Package / Case
120-MQFP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HSP50214BVCZ
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Quantity:
1 001
NOTE:
In burst systems (such as TDMA), time resolution is needed
for quickly identifying the optimum sample point. The timing
is adjusted by shifting the decimation in the DSP μP to the
closest sample. Use of timing error in this way may yield a
faster acquisition than a phase-locked loop coherent bit
synchronization. Finding the optimum sample point
minimizes intersymbol interference.
Fine time resolution is needed in CDMA systems to resolve
different multipath rays. In CDMA systems, the demands on
the programmable FIR can only be relieved by the
resampler/interpolation halfband filters. Assume the chip rate
for a baseband CDMA system is 1.2288MHz and PROCCLK
FIGURE 24C. POLYPHASE RESAMPLER FILTER EXPANDED
Bypass
Polyphase Filter
Polyphase and
1 Halfband
Filter
Polyphase and
2 Halfband
Filters
1 Halfband
Filter
2 Halfband
Filters
3. This frequency is set by the Resampler NCO.
TABLE 10. POLYPHASE AND INTERPOLATING HALFBAND
-10
-1
-2
-3
-4
-5
-6
-7
-8
-9
2
1
0
MODE
FILTER MAXIMUM CLOCKING RATES
RESOLUTION PASSBAND FREQUENCY
RESPONSE
CYCLES
CLOCK
FREQUENCY (RELATIVE TO f
13
23
17
0
6
7
RE-SAMPLER
55.00
55/6 = 9.17
55/13 = 4.23
55/23 = 2.39
55/7 = 7.86
55/17 = 3.24
28
INPUT
(MHz)
RATE
POLATION
INTER-
RATE
S
2
4
2
4
-
-
)
OUTPUT
(Note 3)
(Note 3)
(Note 3)
RATE
(MHz)
55.00
15.72
12.94
9.17
9.56
8.46
HSP50214B
is limited to 55MHz. Using the symmetric filter pre-sum
approach, PROCCLK limits the programmable FIR to
110MIPS (millions of instructions per second) effective due to
symmetry. If the CDMA filter (loaded into the programmable
FIR Section) requires an impulse response with a span of 12
chips, the filter at 2x the chip-rate would need 24 taps. The 24
taps would translate into 59MIPS = (1.2288MHz)(2)(24). To
get the same filtering at 8x the chip rate would require
944MIPS = (1.2288MHz)(8)(96). Direct 8x filtering can not be
accomplished with the programmable filter alone because
944MIPS are much greater that the 60MIPs effective limit set
by PROCCLK. It is necessary to decimate down to 2x the chip
rate to get a realistic number of filter taps. Both interpolation
halfband filters are then used to obtain the 8x CDMA output.
944MIPS is a lot of MIPS. The HSP50214B gets the
equivalent processing by decimating down and interpolating
backup.
Timing NCO
The Timing NCO is very similar to the carrier NCO Phase
Accumulator Section. It provides the NCO driven sample
pulse and associated phase information to the resampling
filter process described in the Re-sampler Filter Section. The
Timing NCO does not include the SIN/COS Section found in
the Carrier NCO. The top level block diagram is shown in
Figure 26.
PROCCLK
NV = INVALID MODE
FIGURE 25. GENERATING DATA READY PULSES FOR
POLYPHASE
RESAMPLER
THIS BLOCK GENERATES EXTRA
DATA READY PULSES FOR THE
NEW OUTPUTS FROM THE
INTERPOLATION PROCESS.
RESAMPLER
FILTER
NCO
OUTPUT DATA
PROCCLK/N
HALFBAND
FILTER #1
PULSE DELAY
COUNTER
PULSE
DELAY
HALFBAND
FILTER #2
0
0
0
0
1
1
1
1
0 0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
# EXTRA
0 BYPASS
0
1
1
3 (NV)
3
3
PULSES
May 1, 2007
FN4450.4