LMV712LD National Semiconductor, LMV712LD Datasheet - Page 10

• Manufacturer Part Number: LMV712LD
• Description: IC,Operational Amplifier,DUAL,BICMOS,LLCC,10PIN,PLASTIC
• Manufacturer: National Semiconductor

Specifications of LMV712LD

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

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Application Information
Theory of Operation
The LMV712 dual op amp is derived from the LMV711 single
op amp. Figure 1 contains a simplified schematic of one
channel of the LMV712.
Rail-to-Rail input is achieved by using in parallel, one NMOS
differential pair (MN1 and MN2) and one PMOS differential
pair (MP1 and MP2). When the common mode input voltage
(V
off. When V
PMOS pair is on. When V
logic decides how much current each differential pair will get.
This special logic ensures stable and low distortion amplifier
operation within the entire common mode voltage range.
Because both input stages have their own offset voltage
(V
comes a function of V
above V
Performance Characteristics section. Caution should be
taken in situations where input signal amplitude is compa-
rable to V
In these situations, it is necessary for the input signal to
avoid the crossover point.
The current coming out of the input differential pairs gets
mirrored through two folded cascode stages (Q1, Q2, Q3,
Q4) into the "class AB control" block. This circuitry generates
voltage gain, defines the op amp’s dominant pole and limits
the maximum current flowing at the output stage. MN3 intro-
duces a voltage level shift and acts as a high impedance to
low impedance buffer.
The output stage is composed of a PMOS and a NPN
transistor in a common source/emitter configuration, deliver-
ing a rail-to-rail output excursion.
CM
OS
) characteristic, the offset voltage of the LMV712 be-
) is near V
−
. Refer to the "V
OS
CM
value and/or the design requires high accuracy.
+
, the NMOS pair is on and the PMOS pair is
is near V
CM
. V
CM
−
OS
, the NMOS pair is off and the
OS
is between V
vs. V
has a crossover point at 1.4V
CM
" curve in the Typical
+
and V
−
, internal
FIGURE 1.
10
The MN4 transistor ensures that the LMV712 output remains
near V
Shutdown Pin
The LMV712 offers independent shutdown pins for the dual
amplifiers. When the shutdown pin is tied low, the respective
amplifier shuts down and the supply current is reduced to
less than 1µA. In shutdown mode, the amplifier’s output level
stays at V
1.5V to 2.7V is applied to the shutdown pin, the amplifier is
enabled. As the amplifier is coming out of the shutdown
mode, the output waveform ramps up without any glitch. This
is demonstrated in Figure 2.
−
when the amplifier is in shutdown mode.
−
. In a 2.7V operation, when a voltage between
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