LMV712LD National Semiconductor, LMV712LD Datasheet - Page 11

• Manufacturer Part Number: LMV712LD
• Description: IC,Operational Amplifier,DUAL,BICMOS,LLCC,10PIN,PLASTIC
• Manufacturer: National Semiconductor

Specifications of LMV712LD

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Application Information
A glitch-free output waveform is highly desirable in many
applications, one of which is power amplifier control loops. In
this application, the LMV712 is used to drive the power
amplifier’s power control. If the LMV712 did not have a
smooth output ramp during turn on, it would directly cause
the power amplifier to produce a glitch at its output. This
adversely affects the performance of the system.
To enable the amplifier, the shutdown pin must be pulled
high. It should not be left floating in the event that any
leakage current may inadvertently turn off the amplifier.
Printed Circuit Board Consideration
To properly bypass the power supply, several locations on a
printed circuit board need to be considered. A 6.8µF or
greater tantalum capacitor should be placed at the point
where the power supply for the amplifier is introduced onto
the board. Another 0.1µF ceramic capacitor should be
placed as close as possible to the power supply pin of the
amplifier. If the amplifier is operated in a single power supply,
only the V
If the amplifier is operated in a dual power supply, both V
and V
It is good practice to use a ground plane on a printed circuit
board to provide all components with a low inductive ground
connection.
Surface mount components in 0805 size or smaller are
recommended in the LMV712 application circuits. Designers
can take advantage of the micro SMD, MSOP and LLP
miniature sizes to condense board layout in order to save
space and reduce stray capacitance.
Capacitive Load Tolerance
The LMV712 can directly drive 200pF in unity-gain without
oscillation. The unity-gain follower is the most sensitive con-
figuration to capacitive loading. Direct capacitive loading
reduces the phase margin of amplifiers. The combination of
the amplifier’s output impedance and the capacitive load
−
pins need to be bypassed.
+
pin needs to be bypassed with a 0.1µF capacitor.
FIGURE 2.
(Continued)
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induces phase lag. This results in either an under-damped
pulse response or oscillation. To drive a heavier capacitive
load, Figure 3 can be used.
In Figure 3, the isolation resistor R
C
margin to the overall system. The desired performance de-
pends on the value of R
value, the more stable V
degraded when the R
resistor in Figure 3, the output voltage would be divided by
R
The circuit in Figure 4 is an improvement to the one in Figure
3 because it provides DC accuracy as well as AC stability. In
this circuit, R
forward techniques to connect V
to counteract the loss of phase margin by feeding the high
frequency component of the output signal back to the ampli-
fier’s inverting input, thereby preserving phase margin in the
overall feedback loop. Increased capacitive drive is possible
by increasing the value of C
pulse response.
Latchup
CMOS devices tend to be susceptible to latchup due to their
internal parasitic SCR (silicon controlled rectifier) effects.
The input and output pins look similar to the gate of the SCR.
There is a minimum current required to trigger the SCR gate
lead. The LMV712 is designed to withstand 150mA surge
current on all the pins. Some resistive method should be
used to isolate any capacitance from supplying excess cur-
rent to the pins. In addition, like an SCR, there is a minimum
holding current for any latchup mode. Limiting current to the
supply pins will also inhibit latchup susceptibility.
L
ISO
form a pole to increase stability by adding more phase
and the load resistor.
F
provides the DC accuracy by using feed-
ISO
FIGURE 3.
FIGURE 4.
OUT
ISO
gets bigger. If there were a load
F
. The bigger the R
. This in turn will slow down the
will be. But the DC accuracy is
IN
ISO
to R
and the load capacitor
L
. C
10137032
F
and R
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ISO
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