MF10CCWM National Semiconductor, MF10CCWM Datasheet - Page 6

• Manufacturer Part Number: MF10CCWM
• Description: IC,FILTER,AP/BP/HP/LP/NOTCH,CMOS,SOP,20PIN,PLASTIC
• Manufacturer: National Semiconductor

Specifications of MF10CCWM

• Rohs Compliant: NO

Pin Descriptions
LSh(9)
CLKA(10)
CLKB(11)
50 100 CL(12)
AGND(15)
Level shift pin it accommodates various
clock levels with dual or single supply
operation With dual
MF10 can be driven with CMOS clock
levels (
tied to the system ground If the same
supplies as above are used but only TTL
clock levels derived from 0V to
supply are available the LSh pin should
be tied to the system ground For single
supply operation (0V and
V
the system ground
should be biased at
pin should also be tied to the system
ground for TTL clock levels LSh should
be biased at
els in 10V single-supply applications
Clock inputs for each switched capaci-
tor filter building block They should both
be of the same level (TTL or CMOS)
The level shift (LSh) pin description dis-
cusses how to accommodate their lev-
els The duty cycle of the clock should
be close to 50% especially when clock
frequencies above 200 kHz are used
This allows the maximum time for the
internal op-amps to settle which yields
optimum filter operation
By tying this pin high a 50 1 clock-to-fil-
ter-center-frequency ratio is obtained
Tying this pin at mid-supplies (i e analog
ground with dual supplies) allows the fil-
ter to operate at a 100 1 clock-to-cen-
ter-frequency ratio When the pin is tied
low (i e negative supply with dual sup-
plies) a simple current limiting circuit is
triggered to limit the overall supply cur-
rent down to about 2 5 mA The filtering
action is then aborted
This is the analog ground pin This pin
should be connected to the system
ground for dual supply operation or bi-
ased to mid-supply for single supply op-
eration For a further discussion of mid-
supply biasing techniques see the Appli-
cations Information (Section 3 2) For
optimum filter performance a ‘‘clean’’
ground must be provided
A
b
V
g
D
(Continued)
b
5V) and the LSh pin should be
pins should be connected to
a
5V for CMOS clock lev-
g
a
5V supplies the
the AGND pin
5V and the LSh
a
10V) the
a
5V
6
(Figure 1)
(Figure 10)
(Figure 1) The value of Q determines the shape of the 2nd
(Figure 2)
1 0 Definition of Terms
f
pin 10 or 11
f
pole pair f
MF10 and is the frequency of maximum bandpass gain
f
notch outputs
f
pair if any If f
observed as the frequency of a notch at the allpass output
Q ‘‘quality factor’’ of the 2nd order filter Q is measured at
the bandpass outputs of the MF10 and is equal to f
by the
order filter responses as shown in Figure 6
Q
if any Q
written
H
where Q
H
H
H
f
H
and as f
above and below the center frequency (Figure 4) When the
low-frequency gain differs from the high-frequency gain as
in modes 2 and 3a (Figures 11 and 8) the two quantities
below are used in place of H
H
H
CLK
CLK
O
notch
z
AP
OBP
OLP
OHP
ON
ON1
ON2
Z
the center frequency of the second order complex zero
center frequency of the second order function complex
the quality factor of the second order complex zero pair
(s)
2 (Figure 3)
the gain (in V V) of the notch output as f
the frequency of the external clock signal applied to
the gain (in V V) of the lowpass output as f
the gain (in V V) of the notch output as f
the gain (in V V) of the notch output as f
the gain (in V V) of the bandpass output at f
e
the gain (in V V) of the highpass output as f
the frequency of minimum (ideally zero) gain at the
b
Z
Z
3 dB bandwidth of the 2nd order bandpass filter
H
e
is related to the allpass characteristic which is
O
OAP
Q for an all-pass response
is measured at the bandpass outputs of the
z
f
s
CLK
is different from f
2
s
a
2
2 when the notch filter has equal gain
b
s
Q
s
O
Q
a
Z
O
a
ON
O 2
O
O 2
and if Q
Z
is high it can be
O
f
divided
e
CLK
0 Hz
0 Hz
0 Hz
f
O
2