PIC12LC671-04I/MF Microchip Technology, PIC12LC671-04I/MF Datasheet - Page 34

• Manufacturer Part Number: PIC12LC671-04I/MF
• Description: 8 PIN, 1.75KB OTP, 128 RAM, 6 I/O,
• Manufacturer: Microchip Technology
• Series: PIC® 12Cr

Specifications of PIC12LC671-04I/MF

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 1.75KB (1K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DFN
• Processor Series: PIC12LC
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 8
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC12LC67104I/MF

PIC12C67X
6.1.5
The EEPROM, when addressed, will generate an
acknowledge after the reception of each byte. The pro-
cessor must generate an extra clock pulse which is
associated with this acknowledge bit.
FIGURE 6-1:
FIGURE 6-2:
DS30561B-page 34
Note:
Data Bus
Data Bus
ACKNOWLEDGE
Acknowledge bits are not generated if an
internal programming cycle is in progress.
BLOCK DIAGRAM OF GPIO6 (SDA LINE)
BLOCK DIAGRAM OF GPIO7 (SCL LINE)
Read
GPIO
Read
GPIO
Write
GPIO
Write
GPIO
Output Latch
Output Latch
Input Latch
D
Q
D
Q
CK
CK
Reset
EN
EN
EN
EN
CK
CK
D
Q
D
Q
ltchpin
ltchpin
Schmitt Trigger
Schmitt Trigger
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. The processor must signal an end of data to
the EEPROM by not generating an acknowledge bit on
the last byte that has been clocked out of the EEPROM.
In this case, the EEPROM must leave the data line
HIGH to enable the processor to generate the STOP
condition (Figure 6-4).
P
V
V
DD
P
N
DD
1999 Microchip Technology Inc.
To EEPROM SDA
Pad
To EEPROM SCL
Pad