PIC16F648A-E/SO Microchip Technology, PIC16F648A-E/SO Datasheet - Page 74
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,18PIN,PLASTIC](/photos/6/76/67656/150-18-soic_sml.jpg)
PIC16F648A-E/SO
Manufacturer Part Number
PIC16F648A-E/SO
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,18PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F627A-IP.pdf
(180 pages)
3.PIC16F627A-IP.pdf
(8 pages)
4.PIC16F627A-IP.pdf
(22 pages)
Specifications of PIC16F648A-E/SO
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
18-SOIC (7.5mm Width)
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SCI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
16
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
I3DBF648 - BOARD DAUGHTER ICEPIC3
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F648A-E/SO
Manufacturer:
INTEL
Quantity:
5
PIC16F627A/628A/648A
REGISTER 12-2:
DS40044G-page 74
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
RCSTA – RECEIVE STATUS AND CONTROL REGISTER (ADDRESS: 18h)
bit 7
SPEN: Serial Port Enable bit
(Configures RB1/RX/DT and RB2/TX/CK pins as serial port pins when bits TRISB<2:1> are set)
1 = Serial port enabled
0 = Serial port disabled
RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
SREN: Single Receive Enable bit
Asynchronous mode:
Synchronous mode - master:
Synchronous mode - slave:
CREN: Continuous Receive Enable bit
Asynchronous mode:
Synchronous mode:
ADEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
Asynchronous mode 8-bit (RX9 = 0):
Synchronous mode
FERR: Framing Error bit
1 = Framing error (Can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
OERR: Overrun Error bit
1 = Overrun error (Can be cleared by clearing bit CREN)
0 = No overrun error
RX9D: 9th bit of received data (Can be parity bit)
Legend:
R = Readable bit
-n = Value at POR
R/W-0
SPEN
1 = Enables address detection, enable interrupt and load of the receive buffer when RSR<8>
0 = Disables address detection, all bytes are received, and ninth bit can be used as parity bit
Unused in this mode
Unused in this mode
Don’t care
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Unused in this mode
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
1 = Enables continuous receive
0 = Disables continuous receive
is set
R/W-0
RX9
R/W-0
SREN
W = Writable bit
‘1’ = Bit is set
R/W-0
CREN
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
ADEN
FERR
© 2009 Microchip Technology Inc.
R-0
x = Bit is unknown
OERR
R-0
RX9D
R-x
bit 0