PIC16F73-E/SP Microchip Technology, PIC16F73-E/SP Datasheet - Page 101
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PIC16F73-E/SP
Manufacturer Part Number
PIC16F73-E/SP
Description
28 PIN, 7KB STD FLASH, 192 RAM, 22 I/O,
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F818-ISO.pdf
(6 pages)
4.PIC16F73-ISP.pdf
(174 pages)
5.PIC16F73-ISP.pdf
(14 pages)
6.PIC16F73-ISP.pdf
(12 pages)
Specifications of PIC16F73-E/SP
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
28-DIP (0.300", 7.62mm)
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
192 B
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
22
Number Of Timers
3 bit
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000, DM163022
Minimum Operating Temperature
- 40 C
On-chip Adc
5 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
PIC16F73E/SP
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F818-ISO PDF datasheet #3
- PIC16F73-ISP PDF datasheet #4
- PIC16F73-ISP PDF datasheet #5
- PIC16F73-ISP PDF datasheet #6
- Current page: 101 of 688
- Download datasheet (3Mb)
6.2.6
1997 Microchip Technology Inc.
Program Memory Paging
Some devices have program memory sizes greater then 2K words, but the CALL and GOTO
instructions only have a 11-bit address range. This 11-bit address range allows a branch within
a 2K program memory page size. To allow CALL and GOTO instructions to address the entire 1K
program memory address range, there must be another two bits to specify the program memory
page. These paging bits come from the PCLATH<4:3> bits
GOTO instruction, the user must ensure that page bits (PCLATH<4:3>) are programmed so that
the desired program memory page is addressed
tions is executed, the entire 13-bit PC is POPed from the stack. Therefore, manipulation of the
PCLATH<4:3> is not required for the return instructions.
Example 6-1
assumes that PCLATH is saved and restored by the interrupt service routine (if interrupts are
used).
Example 6-1: Call of a Subroutine in Page1 from Page0
SUB1_P1:
Note:
ORG 0x500
BSF
CALL
ORG 0x900
RETURN
:
:
:
Section 6. Memory Organization
Devices with program memory sizes 2K words and less, ignore both paging bits
(PCLATH<4:3>), which are used to access program memory when more than one
page is available. The use of PCLATH<4:3> as general purpose read/write bits (for
these devices) is not recommended since this may affect upward compatibility with
future products.
Devices with program memory sizes between 2K words and 4K words, ignore the
paging bit (PCLATH<4>), which is used to access program memory pages 2 and 3
(1000h - 1FFFh). The use of PCLATH<4> as a general purpose read/write bit (for
these devices) is not recommended since this may affect upward compatibility with
future products.
shows the calling of a subroutine in page 1 of the program memory. This example
PCLATH,3
SUB1_P1
; Select Page1 (800h-FFFh)
; Call subroutine in Page1 (800h-FFFh)
;
;
;
; called subroutine Page1 (800h-FFFh)
;
; return to Call subroutine in Page0 (000h-7FFh)
;
(Figure
6-2). When one of the return instruc-
(Figure
6-2). When doing a CALL or
DS31006A-page 6-7
6
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