PIC16F77-I/ML Microchip Technology, PIC16F77-I/ML Datasheet - Page 55

44 PIN, 14KB STD FLASH, 368 RAM, 33 I/O,

PIC16F77-I/ML

Manufacturer Part Number
PIC16F77-I/ML
Description
44 PIN, 14KB STD FLASH, 368 RAM, 33 I/O,
Manufacturer
Microchip Technology
Series
PIC® 16Fr

Specifications of PIC16F77-I/ML

Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
368 B
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
33
Number Of Timers
3 bit
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000, DM163022
Minimum Operating Temperature
- 40 C
On-chip Adc
8
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN444-1001 - DEMO BOARD FOR PICMICRO MCU
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
8.0
Each Capture/Compare/PWM (CCP) module contains
a 16-bit register which can operate as a:
• 16-bit Capture register
• 16-bit Compare register
• PWM Master/Slave Duty Cycle register
Both the CCP1 and CCP2 modules are identical in
operation, with the exception being the operation of the
special event trigger. Table 8-1 and Table 8-2 show the
resources and interactions of the CCP module(s). In
the following sections, the operation of a CCP module
is described with respect to CCP1. CCP2 operates the
same as CCP1, except where noted.
8.1
Capture/Compare/PWM Register1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. The special event trigger is
generated by a compare match and will clear both
TMR1H and TMR1L registers.
TABLE 8-2:
 2002 Microchip Technology Inc.
CCPx Mode CCPy Mode
Capture
Capture
Compare
PWM
PWM
PWM
CAPTURE/COMPARE/PWM
MODULES
CCP1 Module
Capture
Compare
Compare
PWM
Capture
Compare
INTERACTION OF TWO CCP MODULES
Same TMR1 time-base.
Same TMR1 time-base.
Same TMR1 time-base.
The PWMs will have the same frequency and update rate (TMR2 interrupt).
The rising edges are aligned.
None.
None.
8.2
Capture/Compare/PWM Register1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP2CON register controls
the operation of CCP2. The special event trigger is
generated by a compare match; it will clear both
TMR1H and TMR1L registers, and start an A/D conver-
sion (if the A/D module is enabled).
Additional information on CCP modules is available in
the PICmicro™ Mid-Range MCU Family Reference
Manual (DS33023) and in Application Note AN594,
“Using the CCP Modules” (DS00594).
TABLE 8-1:
Interaction
CCP Mode
CCP2 Module
Compare
Capture
PWM
CCP MODE - TIMER
RESOURCES REQUIRED
PIC16F7X
Timer Resource
DS30325B-page 53
Timer1
Timer1
Timer2

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