PIC16F870-E/SO Microchip Technology, PIC16F870-E/SO Datasheet - Page 267
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC16F870-E/SO
Manufacturer Part Number
PIC16F870-E/SO
Description
28 PIN, 3.5KB ENH FLASH, 128 RAM, 22 I/O,
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F870-ISO.pdf
(172 pages)
4.PIC16F870-ISO.pdf
(6 pages)
Specifications of PIC16F870-E/SO
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
I3-DB16F871 - BOARD DAUGHTER ICEPIC3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F870-ISO PDF datasheet #3
- PIC16F870-ISO PDF datasheet #4
- Current page: 267 of 688
- Download datasheet (3Mb)
16.4.1
1997 Microchip Technology Inc.
Slave Mode
In slave mode, the SCL and SDA pins must be configured as inputs (TRIS bits set). The SSP
module will override the input state with the output data when required (slave-transmitter).
When an address is matched or the data transfer after an address match is received, the hard-
ware automatically will generate the acknowledge (ACK) pulse, and then load the SSPBUF reg-
ister with the received value currently in the SSPSR register.
There are certain conditions that will cause the SSP module not to give this ACK pulse. These
are if either (or both):
a)
b)
In this case, the SSPSR register value is not loaded into the SSPBUF, but bit SSPIF and SSPOV
bits are set.
tus of the BF and SSPOV bits. The shaded cells show the condition where user software did not
properly clear the overflow condition. The BF flag bit is cleared by reading the SSPBUF register
while the SSPOV bit is cleared through software.
The SCL clock input must have a minimum high and low time for proper operation. The high and
low times of the I
parameter 100
The buffer full bit, BF (SSPSTAT<0>), was set before the transfer was received.
The overflow bit, SSPOV (SSPCON<6>), was set before the transfer was received.
Table 16-2
and
2
C specification as well as the requirement of the SSP module are given in
parameter 101
shows what happens when a data transfer byte is received, given the sta-
of the
“Electrical Specifications”
Section 16. BSSP
section.
DS31016A-page 16-17
16
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