PIC16F870-E/SO Microchip Technology, PIC16F870-E/SO Datasheet - Page 304
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC16F870-E/SO
Manufacturer Part Number
PIC16F870-E/SO
Description
28 PIN, 3.5KB ENH FLASH, 128 RAM, 22 I/O,
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F870-ISO.pdf
(172 pages)
4.PIC16F870-ISO.pdf
(6 pages)
Specifications of PIC16F870-E/SO
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
I3-DB16F871 - BOARD DAUGHTER ICEPIC3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F870-ISO PDF datasheet #3
- PIC16F870-ISO PDF datasheet #4
- Current page: 304 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
17.4.5
DS31017A-page 17-28
SDA
SCL
Master Mode
Master mode of operation is supported by interrupt generation on the detection of the START and
STOP conditions. The STOP (P) and START (S) bits are cleared from a reset or when the SSP
module is disabled. Control of the I
with both the S and P bits clear.
In master mode the SCL and SDA lines are manipulated by the SSP hardware.
The following events will cause SSP Interrupt Flag bit, SSPIF, to be set (SSP Interrupt if enabled):
• START condition
• STOP condition
• Data transfer byte transmitted/received
• Acknowledge Transmit
• Repeated Start
Figure 17-17: SSP Block Diagram (I 2 C Master Mode)
SDA in
Bus Collision
SCL in
Read
MSb
Write collision detect
end of XMIT/RCV
Start bit, Stop bit,
State counter for
Clock Arbitration
Start bit detect
Stop bit detect
Acknowledge
Generate
SSPBUF
SSPSR
Preliminary
2
C bus may be taken when the P bit is set, or the bus is idle
LSb
Write
clock
data bus
shift
Internal
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
1997 Microchip Technology Inc.
SSPADD<6:0>
SSPM3:SSPM0
Baud
rate
generator
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