PIC16HV785-E/ML Microchip Technology, PIC16HV785-E/ML Datasheet
PIC16HV785-E/ML
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... Two-Phase Asynchronous Feedback PWM Dual High-Speed Comparators and © 2008 Microchip Technology Inc. PIC16F785/HV785 Data Sheet 20-Pin Flash-Based, 8-Bit CMOS Microcontroller with Dual Operational Amplifiers DS41249E ...
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... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Register, Prescaler and Postscaler • Capture, Compare, PWM module: - 16-bit Capture, max resolution 12 Compare, max resolution 200 ns - 10-bit PWM with 1 output channel, max frequency 20 kHz • In-Circuit Serial Programming pins • Shunt Voltage Regulator (PIC16HV785 only volt regulation - shunt range ) DD TM (ICSP TM ...
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... PIC16F785/HV785 Program Data Memory Memory Device Flash SRAM EEPROM (words) (bytes) (bytes) PIC16F785 2048 128 256 PIC16HV785 2048 128 256 Dual in Line Pin Diagram 20-pin PDIP, SOIC, SSOP RA5/T1CKI/OSC1/CLKIN RA4/AN3/T1G/OSC2/CLKOUT RA3/MCLR/V RC5/CCP1 RC4/C2OUT/PH2 RC3/AN7/C12IN3-/OP1 RC6/AN8/OP1- RC7/AN9/OP1+ RB7/SYNC TABLE 1: DUAL IN LINE PIN SUMMARY ...
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... C2OUT RC5 2 — — RC6 5 AN8 — RC7 6 AN9 — — 18 — — — 17 — — Note 1: Input only. 2: Open drain. © 2008 Microchip Technology Inc. PIC16F785/HV785 RA1/AN1/C12IN0-/ RA2/AN2/T0CKI/INT/C1OUT 14 RC0/AN4/C2IN RC1/AN5/C12IN1-/PH1 RC2/AN6/C12IN2-/OP2 PIC16F785/HV785 Op PWM Timers CCP Amps — — ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS41249E-page 4 © 2008 Microchip Technology Inc. ...
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... Oscillator Decode and Control OSC1/CLKIN Timing OSC2/CLKOUT Generation 8 MHz Internal Oscillator T1G T1CKI Timer0 Timer1 T0CKI Analog-to-Digital Converter © 2008 Microchip Technology Inc. PIC16F785/HV785 INT 13 Data Bus Program Counter RAM 8-Level Stack 128 bytes (13-bit) File Registers RAM Addr 9 ADDR MUX ...
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... AN Op Amp 2 non-inverting input TTL OD PORTB I/O. Open drain output TTL CMOS PORTB I/O ST CMOS Master PWM Sync output or slave PWM Sync input TTL CMOS PORTC I/O AN — A/D Channel 4 input AN — Comparator 2 non-inverting input Description © 2008 Microchip Technology Inc. ...
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... RC7 AN9 OP1 Legend: TTL = TTL input buffer Schmitt Trigger input buffer Analog Open Drain output High Voltage © 2008 Microchip Technology Inc. PIC16F785/HV785 Input Output Type Type TTL CMOS PORTC I/O AN — A/D Channel 5 input AN — Comparator 1 and 2 inverting input — ...
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... PIC16F785/HV785 NOTES: DS41249E-page 8 © 2008 Microchip Technology Inc. ...
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... Stack Level 2 Stack Level 8 Reset Vector Interrupt Vector On-chip Program Memory © 2008 Microchip Technology Inc. PIC16F785/HV785 2.2 Data Memory Organization The data memory (see Figure 2-2) is partitioned into four banks, which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR) ...
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... TRISC 187h 188h 189h PCLATH 18Ah INTCON 18Bh PIE1 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h 1EFh accesses 1F0h Bank 0 1FFh Bank 3 © 2008 Microchip Technology Inc. ...
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... Unimplemented locations read as ‘0’ unchanged unknown value depends on condition, shaded = unimplemented Note 1: Port pins with analog functions controlled by the ANSEL0 and ANSEL1 registers will read ‘0’ immediately after a Reset even though the data latches are either undefined (POR) or unchanged (other Resets). © 2008 Microchip Technology Inc. PIC16F785/HV785 Bit 5 Bit 4 Bit 3 ...
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... IOCA1 IOCA0 37,114 --00 0000 — — CVROE — 73,114 --00 000- VR1 VR0 72,114 000- 0000 EEDAT1 EEDAT0 0000 0000 103,114 EEADR1 EEADR0 0000 0000 103,114 WR RD ---- x000 104,114 ---- ---- 104,114 81,114 xxxx xxxx — — 84,114 -000 ---- © 2008 Microchip Technology Inc. ...
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... Unimplemented locations read as ‘0’ unchanged unknown value depends on condition, shaded = unimplemented Note 1: Port pins with analog functions controlled by the ANSEL0 and ANSEL1 registers will read ‘0’ immediately after a Reset even though the data latches are either undefined (POR) or unchanged (other Resets). © 2008 Microchip Technology Inc. PIC16F785/HV785 Bit 5 Bit 4 Bit 3 ...
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... Microchip Technology Inc. ...
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... For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register. © 2008 Microchip Technology Inc. PIC16F785/HV785 For example, CLRF STATUS will clear the upper three bits and set the Z bit ...
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... PSA bit to ‘1’ in the OPTION Reg- ister. See Section 5.4 “Prescaler”. R/W-1 R/W-1 R/W-1 T0SE PSA U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ( 128 256 1 : 128 R/W-1 R/W-1 PS2 PS1 PS0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... None of the PORTA <5:0> pins have changed state Note 1: IOCA register must also be enabled. 2: T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before clear- ing T0IF bit. © 2008 Microchip Technology Inc. PIC16F785/HV785 Note: Interrupt flag bits are set when an interrupt ...
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... Disables the Timer1 overflow interrupt DS41249E-page 18 Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. R/W-0 R/W-0 R/W-0 C2IE C1IE OSFIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 TMR2IE TMR1IE bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... Timer2 to PR2 match has not occurred bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Timer1 register overflowed (must be cleared in software Timer1 has not overflowed © 2008 Microchip Technology Inc. PIC16F785/HV785 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE, in the INTCON Register) ...
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... A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Note 1: BOREN<1:0> Configuration Word for this bit to control the BOR. DS41249E-page 20 R/W-1 U-0 U-0 (1) — SBOREN — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-x — POR bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... CALL instruction (or interrupt) is executed, the entire 13-bit PC return address is PUSHed onto the stack. Therefore, manipulation of the PCLATH<4:3> bits are not required for the RETURN or RETFIE instructions (which POPs the address from the stack). © 2008 Microchip Technology Inc. PIC16F785/HV785 FIGURE 2-3: PCH 12 ...
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... CONTINUE 0 IRP Bank Select 180h Bank 1 Bank 2 Bank 3 INDIRECT ADDRESSING ;initialize pointer ;to RAM INDF ;clear INDF register FSR ;increment pointer ;all done? NEXT ;no clear next ;yes continue Indirect Addressing File Select Register 7 0 Location Select 1FFh © 2008 Microchip Technology Inc. ...
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... PIC16F785/HV785 CLOCK SOURCE BLOCK DIAGRAM External Oscillator OSC2 Sleep OSC1 Internal Oscillator HFINTOSC 8 MHz LFINTOSC 31 kHz © 2008 Microchip Technology Inc. PIC16F785/HV785 The PIC16F785/HV785 can be configured in one of eight clock modes – External clock with I/O on RA4 – 32.768 kHz Watch Crystal or Ceramic Resonator Oscillator mode. 3. ...
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... Following a wake-up from Sleep mode or (1) CPU Start-up POR, CPU start-up is invoked to allow the CPU to become ready for code execution. 1024 Clock Cycles (OST) 1 μs (approx.) FIGURE 3-2: EXTERNAL CLOCK (EC) MODE OPERATION Clock from Ext. System RA4 © 2008 Microchip Technology Inc. OSC1/CLKIN PIC16F785/HV785 I/O (OSC2) ...
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... Always verify oscillator performance over the V and temperature range that is DD expected for the application. © 2008 Microchip Technology Inc. PIC16F785/HV785 FIGURE 3- Ceramic Resonator Note 1: A series resistor (R ceramic resonators with low drive level. ...
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... Internal Clock ≥ 3.0V) DD < 3.0V) DD RCIO MODE Internal OSC1 Clock PIC16F785/HV785 I/O (OSC2) ≤ 100 kΩ (V ≥ 3.0V) EXT DD 10 kΩ ≤ R ≤ 100 kΩ (V < 3.0V) EXT DD C > EXT ) and capacitor (C ) EXT EXT © 2008 Microchip Technology Inc. ...
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... Two-Speed Start-up is enabled (IESO = 1 and IRCF ≠ 000). The HF Internal Oscillator (HTS) bit, in the OSCCON Register, indicates whether the HFINTOSC is stable or not. © 2008 Microchip Technology Inc. PIC16F785/HV785 3.4.2.1 Calibration Bits The 8 MHz High-frequency Internal Oscillator (HFIN- TOSC) is factory calibrated ...
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... Watchdog Timer (WDT), Fail-Safe Clock Monitor (FSCM) and peripherals, are not affected by the change in frequency. R/W-0 R/W-0 R/W-0 TUN4 TUN3 TUN2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 TUN1 TUN0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... Note: Following any Reset, the IRCF bits are set to ‘110’ and the frequency selection is forced to 4 MHz. The user can modify the IRCF bits to select a different frequency. © 2008 Microchip Technology Inc. PIC16F785/HV785 3.4.5 HF AND LF INTOSC CLOCK SWITCH TIMING When switching between the LFINTOSC and the HFIN- TOSC, the new oscillator may already be shut down to save power. If this is the case, there μ ...
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... CHECKING EXTERNAL/INTERNAL CLOCK STATUS Checking the state of the OSTS bit in the OSCCON Register) will confirm if the PIC16F785/HV785 is run- ning from the external clock source as defined by the F bits in the Configuration Word (CONFIG) or the OSC internal oscillator. © 2008 Microchip Technology Inc. ...
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... OSFIE bit in the PIE1 Reg- ister is set. The device will then switch the system clock to the internal oscillator. The system clock will continue to come from the internal oscillator unless the external clock recovers and the Fail-Safe condition is exited. © 2008 Microchip Technology Inc. PIC16F785/HV785 ...
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... Reset or Sleep). After an appropriate amount of time, the user should check the OSTS bit in the OSCCON Register to ver- ify the oscillator start-up and system clock switchover has successfully completed. DS41249E-page 32 Oscillator Failure Failure Detected CM Test CM Test © 2008 Microchip Technology Inc. ...
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... Internal oscillator is used for system clock 0 = Clock source defined by FOSC<2:0> Note 1: Bit resets to ‘0’ with Two-Speed Start-up and LP selected as the Oscillator mode or Fail-Safe mode is enabled, otherwise this bit resets to ‘1’ © 2008 Microchip Technology Inc. PIC16F785/HV785 R/W-0 R-q R-0 ...
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... C1IE OSFIE TMR2IE C2IF C1IF OSFIF TMR2IF Value on Value on all Bit 0 POR, BOR other Resets FOSC0 — — SCS -110 q000 -110 q000 TUN0 ---0 0000 ---u uuuu TMR1IE 0000 0000 0000 0000 TMR1IF 0000 0000 0000 0000 © 2008 Microchip Technology Inc. ...
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... Port pin is less than V Note 1: Data latches are unknown after a POR, but each port bit reads ‘0’ when the corresponding analog select bit is ‘1’ (see Register 12-1). © 2008 Microchip Technology Inc. PIC16F785/HV785 The TRISA register controls the direction of the PORTA pins, even when they are being used as analog inputs ...
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... Register. The weak pull-up on RA3 is automatically enabled when RA3 is configured as MCLR. R/W-1 R/W-1 R/W-1 (4) (4) (3) WPUA4 WPUA3 WPUA2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 TRISA1 TRISA0 bit Bit is unknown (1) R/W-1 R/W-1 WPUA1 WPUA0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... Interrupt-on-change disabled Note 1: Global interrupt enable (GIE) must be enabled for individual interrupts to be recognized. 2: IOCA<5:4> always reads ‘1’ in XT, HS and LP OSC modes. © 2008 Microchip Technology Inc. PIC16F785/HV785 This interrupt can wake the device from Sleep. The user, in the Interrupt Service Routine, clears the inter- ...
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... FIGURE 4-2: VR OUT VROE*VREN CVROE ANS1 Data Bus WPUA Weak RD WPUA PORTA TRISA I/O pin RD TRISA PORTA IOCA RD IOCA Q1 Interrupt-on- change Q3 To Comparators To A/D Converter /ICSPCLK REF BLOCK DIAGRAM OF RA1 V DD Weak Q Q RAPU I/O pin PORTA © 2008 Microchip Technology Inc. ...
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... Interrupt-on- EN Change RD PORTA To TMR0 To INT To A/D Converter © 2008 Microchip Technology Inc. PIC16F785/HV785 4.2.3.4 Figure 4-4 shows the diagram for this pin. The RA3 pin is configurable to function as one of the following: • General purpose input • Master Clear Reset with weak pull-up ...
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... To TMR1 or CLKGEN Note 1: CLK modes are XT, HS, LP and LPTMR1. 2: When using Timer1 with LP oscillator, the RA5/T1CKI/OSC1/CLKIN BLOCK DIAGRAM OF RA5 INTOSC Mode (1) CLK modes Weak Q RAPU V Oscillator DD Circuit OSC2 Q I/O pin INTOSC Mode ( PORTA Schmitt Trigger is bypassed. © 2008 Microchip Technology Inc. ...
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... TMR1GE T1CKPS1 TRISA — — TRISA5 WPUA — — WPUA5 Legend unknown unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. © 2008 Microchip Technology Inc. PIC16F785/HV785 Bit 4 Bit 3 Bit 2 Bit 1 ANS4 ANS3 ANS2 ANS1 C1POL C1SP ...
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... PORTB ;Bank 1 ;digital I/O - RB4 ;digital I/O - RB5 ;Set RB<5:4> as inputs ;and set RB<7:6> ;as outputs ;Bank 0 U-0 U-0 U-0 — — — bit Bit is unknown U-0 U-0 U-0 — — — bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... PORTB TRISB ANS10 (RB4) ANS11 (RB5) RD TRISB PORTB To A/D Converter To Op Amp 2 © 2008 Microchip Technology Inc. PIC16F785/HV785 4.3.1.3 RB6 The RB6 pin is configurable to function as the following: • Open drain general purpose I/O FIGURE 4-8: Data Bus PORTB TRISB RD TRISB RD PORTB 4 ...
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... RB4 — — — BLANK1 SYNC1 SYNC0 PH2EN TRISB4 — — — Value on Value on all Bit 0 POR, BOR other Resets ANS8 ---- 1111 ---- 1111 — 0--- ---- 0--- ---- — xxxx ---- uuuu ---- PH1EN 0000 0000 0000 0000 — 1111 ---- 1111 ---- © 2008 Microchip Technology Inc. ...
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... TRISC<7:0>: PORTC Tri-State Control bits 1 = PORTC pin configured as an input (tri-stated PORTC pin configured as an output © 2008 Microchip Technology Inc. PIC16F785/HV785 When RC4 or RC5 is configured amp output, the corresponding RC4 or RC5 digital output driver will automatically be disabled regardless of the TRISC<4> ...
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... Analog input to Comparators 1 and 2 • Digital output from the Two-Phase PWM FIGURE 4-11: PH1EN PH1 Data Bus PORTC TRISC RD TRISC RD PORTC To Comparators To A/D Converter V DD I/O Pin V SS BLOCK DIAGRAM OF RC1 I/O Pin V SS ANS5 © 2008 Microchip Technology Inc. ...
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... ANS7 (RC3) RD TRISC PORTC To Comparators To A/D Converter © 2008 Microchip Technology Inc. PIC16F785/HV785 4.4.1.7 RC4/C2OUT/PH2 The RC4 is configurable to function as one of the following: • General purpose I/O • Digital output from Comparator 2 • Digital output from the Two-Phase PWM FIGURE 4-13: C2OE ...
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... D EN Value on Value on all Bit 0 POR, BOR other Resets ANS8 ---- 1111 ---- 1111 CCP1M0 0000 0000 0000 0000 — 0--- ---- 0--- ---- — 0--- ---- 0--- ---- RC0 xxxx xxxx uuuu uuuu PH1EN 0000 0000 0000 0000 TRISC0 1111 1111 1111 1111 © 2008 Microchip Technology Inc. ...
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... INTRC Timer Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION_REG (see Register 2.2.2.3). 2: WDTPS<3:0> are bits in the WDTCON register (see Register 15-2). © 2008 Microchip Technology Inc. PIC16F785/HV785 RA2/AN2/T0CKI/INT/C1OUT. The incrementing edge is determined by the source edge (T0SE) control bit of the OPTION Register. Clearing the T0SE bit selects the rising edge ...
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... TMR0, ; prescale, and ; clock source ; ;Bank 0 Value on Value on all Bit 0 POR, BOR other Resets ANS0 1111 1111 1111 1111 RAIF 0000 0000 0000 0000 PS0 1111 1111 1111 1111 xxxx xxxx uuuu uuuu TRISA0 --11 1111 --11 1111 © 2008 Microchip Technology Inc. ...
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... ST Buffer is low power type when using LP OSC, or high-speed type when using T1CKI. Note 1: Timer1 increments on the rising edge. 2: SYNCC2OUT is the synchronized output from Comparator 2 (See Figure 9-2 on 66). © 2008 Microchip Technology Inc. PIC16F785/HV785 The Timer1 Control register (T1CON), shown in Register 6-1, is used to enable/disable Timer1 and select the various features of the Timer1 module ...
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... Timer1 gate source. Timer1 gate can be inverted using the T1GINV bit of the T1CON Register, whether it originates from the T1G pin or Comparator 2 output. This configures Timer1 to measure either the active high or active low time between events. © 2008 Microchip Technology Inc. ...
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... Enables Timer1 0 = Stops Timer1 Note 1: T1GINV bit inverts the Timer1 gate logic, regardless of source. 2: TMR1GE bit must be set to use either T1G pin or C2OUT, as selected by T1GSS bit (CM2CON1<1>), as a Timer1 gate source. © 2008 Microchip Technology Inc. PIC16F785/HV785 R/W-0 R/W-0 R/W-0 T1CKPS0 ...
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... ANS0 1111 1111 1111 1111 C2SYNC 00-- --10 00-- --10 RAIF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 TMR1IF 0000 0000 0000 0000 TMR1ON 0000 0000 uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu © 2008 Microchip Technology Inc. ...
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... For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register. © 2008 Microchip Technology Inc. PIC16F785/HV785 7.1 Timer2 Operation Timer2 can be used as the PWM time base for the PWM mode of the CCP module ...
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... Value on Value on all Bit 0 POR, BOR other Resets RAIF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 TMR1IF 0000 0000 0000 0000 1111 1111 1111 1111 T2CKPS0 -000 0000 -000 0000 0000 0000 0000 0000 © 2008 Microchip Technology Inc. ...
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... For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register. © 2008 Microchip Technology Inc. PIC16F785/HV785 TABLE 8-1: CCP MODE – TIMER ...
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... CCP module off ; the new prescaler ; move value and CCP ON ;Load CCP1CON with this ; value COMPARE MODE OPERATION BLOCK DIAGRAM Mode Select Set Flag bit CCP1IF (PIR1<5>) 4 CCPR1H CCPR1L S Output Comparator Logic Match R TMR1H TMR1L © 2008 Microchip Technology Inc. ...
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... TRISC6 TRISC5 Legend: – = Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the Capture, Compare or Timer1 module. © 2008 Microchip Technology Inc. PIC16F785/HV785 8.2.4 SPECIAL EVENT TRIGGER In this mode (CCP1M<3:0> = 1011), an internal hardware trigger is generated, which may be used to initiate an action ...
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... Operation”) is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. RC5/CCP1 TRISC<5> PWM PERIOD [ ( ) ] 4 T • • • = PR2 + 1 OSC (TMR2 prescale value) © 2008 Microchip Technology Inc. ...
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... Maximum Resolution (bits) 10 Note 1: Changing duty cycle will cause a glitch. © 2008 Microchip Technology Inc. PIC16F785/HV785 CCPR1L and DC1B<1:0> can be written to at any time, but the duty cycle value is not latched into CCPR1H until after a match between PR2 and TMR2 occurs (i ...
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... RAIF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 TMR1IF 0000 0000 0000 0000 1111 1111 1111 1111 T2CKPS0 -000 0000 -000 0000 0000 0000 0000 0000 TRISC0 --11 1111 --11 1111 © 2008 Microchip Technology Inc. ...
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... AN<7:5,1>. Note: To use AN<7:5,1> as analog inputs the appropriate bits must be programmed to ‘1’ in the ANSEL0 register. © 2008 Microchip Technology Inc. PIC16F785/HV785 Setting C1R of the CM1CON0 Register selects the C1V output of the comparator voltage reference REF module as the reference voltage for the comparator ...
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... When C1ON = 0, the C1 comparator will produce a ‘0’ output to the XOR Gate. 2: Output shown for reference only. For more detail, see Figure 4-3. DS41249E-page MUX 2 Q3*RD_CM1CON0 3 (1) C1ON C1SP C1VN 0 C1 C1VP MUX 1 C1POL C1POL Data Bus EN RD_CM1CON0 Set C1IF PWM Logic CL NRESET C1OE C1OUT (2) RA2/AN2/T0CKI/INT/C1OUT © 2008 Microchip Technology Inc. ...
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... C1CH<1:0>: Comparator C1 Channel Select bits 00 = C1VN of C1 connects to RA1/AN1/C12IN0-/ C1VN of C1 connects to RC1/AN5/C12IN1-/PH1 10 = C1VN of C1 connects to RC2/AN6/C12IN2-/OP2 11 = C1VN of C1 connects to RC3/AN7/C12IN3-/OP1 Note 1: C1OUT will only drive RA2/AN2/T0CKI/INT/C1OUT if: (C1OE = 1) and (C1ON = 1) and (TRISA<2> = 0). © 2008 Microchip Technology Inc. PIC16F785/HV785 R/W-0 R/W-0 R/W-0 C1POL ...
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... Q3*RD_CM2CON0 (1) C2ON 0 C2SP 1 C2VN MUX C2 2 C2VP 3 C2POL 0 From TMR1 MUX Clock 1 C2 OUTPUT STATE VERSUS INPUT CONDITIONS C2POL C2OUT (TRISA<4> = 0). C2POL Data Bus EN RD_CM2CON0 Set C2IF NRESET To PWM Logic C2OUT C2SYNC C20E 0 MUX RC4/C2OUT/PH2 (2) SYNCC2OUT © 2008 Microchip Technology Inc. (3) ...
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... C2CH<1:0>: Comparator C2 Channel Select bits 00 = C2VN of C2 connects to RA1/AN1/C12IN0-/ C2VN of C2 connects to RC1/AN5/C12IN1-/PH1 10 = C2VN of C2 connects to RC2/AN6/C12IN2-/OP2 11 = C2VN of C2 connects to RC3/AN7/C12IN3-/OP1 Note 1: C2OUT will only drive RC4/C2OUT/PH2 if: (C2OE = 1) and (C2ON = 1) and (TRISC<4> = 0). © 2008 Microchip Technology Inc. PIC16F785/HV785 R/W-0 R/W-0 R/W-0 C2POL ...
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... C2SYNC: C2 Output Synchronous Mode bit output is synchronous to falling edge of TMR1 clock output is asynchronous DS41249E-page 68 U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2008 Microchip Technology Inc. R/W-1 R/W-0 T1GSS C2SYNC bit Bit is unknown ...
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... Timer1 by setting the C2SYNC bit when Comparator 2 is used as the Timer1 gate source. This ensures Timer1 does not miss an increment if Comparator 2 changes during an increment. © 2008 Microchip Technology Inc. PIC16F785/HV785 9.3 Comparator Interrupts The comparator interrupt flags are set whenever there is a change in the output value of its respective compar- ator ...
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... V REF tested absolute accuracy of the comparator voltage reference can be found in Table 19-8. CV OUTPUT VOLTAGE REF = VR<3:0> / /4) + (VR<3:0> /32 cannot be realized due from approaching V or REF SS . This allows the comparators SS REF derived and therefore, the DD . The DD © 2008 Microchip Technology Inc. ...
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... COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM 16-1 Analog (1) CVREN CV REF CVROE C1VREN C1V to REF 1 Comparator 1 Input 0 C2VREN C2V to REF 1 Comparator 2 Input 0 Note 1: See Register 10-1, bits 3-0. © 2008 Microchip Technology Inc. PIC16F785/HV785 16 Stages MUX 15 · · · 0 VR3:VR0 VR 1 VRR DS41249E-page 71 ...
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... REF Range Selection bit REF Value Selection 0 ≤ VR<3:0> ≤ 15 REF = (VR<3:0> /24) REF /4) + (VR<3:0> REF DD = 1.2V from VR module REF current. R/W-0 R/W-0 R/W-0 VR2 VR1 VR0 bit Bit is unknown /32) DD circuit is powered down and REF © 2008 Microchip Technology Inc. ...
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... CVROE: Comparator Voltage Reference Output Enable bit (see Figure 10- output on RA1/AN1/C12IN0-/V REF output on RA1/AN1/C12IN0-/V REF bit 0 Unimplemented: Read as ‘0’ Note 1: Buffer amplifier common mode limitations require V 2: VREN is fixed high for PIC16HV785 device. © 2008 Microchip Technology Inc. PIC16F785/HV785 REF R/W-0 R/W-0 R/W-0 VRBB VREN VROE U = Unimplemented bit, read as ‘ ...
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... FIGURE 10-2: VR REFERENCE BLOCK DIAGRAM VREN CV CVROE REF EN Voltage Reference RDY Note 1: Buffered output requires VR 2: VREN is fixed high for PIC16HV785 device. TABLE 10-1: REGISTERS ASSOCIATED WITH COMPARATOR AND VOLTAGE REFERENCE MODULES Name Bit 7 Bit 6 Bit 5 ANSEL0 ANS7 ANS6 ANS5 CM1CON0 ...
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... OPA MODULE BLOCK DIAGRAM RC7/AN9/OP1+ RC6/AN8/OP1- RC3/AN7/C12IN3-/OP1 RB5/AN11/OP2+ RB4/AN10/OP2- RC2/AN6/C12IN2-/OP2 © 2008 Microchip Technology Inc. PIC16F785/HV785 11.2 OPAxCON Register The OPA module is enabled by setting the OPAON bit of the OPAxCON Register. When enabled, OPAON forces the output driver of RC3/AN7/C12IN3-/OP1 for ...
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... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2008 Microchip Technology Inc. U-0 U-0 — — bit Bit is unknown U-0 U-0 — — ...
Page 79
... TRISC7 TRISC6 TRISC5 Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used for the OPA module. © 2008 Microchip Technology Inc. PIC16F785/HV785 Leakage current is a measure of the small source or sink currents on the OPA+ and OPA- inputs. To mini- mize the effect of leakage currents, the effective imped- ances connected to the OPA+ and OPA- inputs should be kept as small as possible and equal ...
Page 80
... PIC16F785/HV785 NOTES: DS41249E-page 78 © 2008 Microchip Technology Inc. ...
Page 81
... RA2/AN2/T0CKI/INT/C1OUT RA4/AN3/T1G/OSC2/CLKOUT RC0/AN4/C2IN+ RC1/AN5/C12IN1-/PH1 RC2/AN6/C12IN2-/OP2 RC3/AN7/C12IN3-/OP1 RC6/AN8/OP1- RC7/AN9/OP1+ RB4/AN10/OP2- RB5/AN11/OP2+ CV REF VR CHS<3:0> Note 1: When ADON = 0 all input channels are disconnected from ADC (no loading). © 2008 Microchip Technology Inc. PIC16F785/HV785 V DD VCFG = 0 V VCFG = 1 REF 0 A/D GO/DONE ADFM (1) ADON V ...
Page 82
... AD 4 MHz 1.25 MHz 1.6 μs (2) 500 ns 1.0 μs (2) 3.2 μs 2.0 μs 6.4 μs 4.0 μs 12.8 μs (3) 8.0 μs (3) 25.6 μs (3) 16.0 μs 51.2 μs (3) (3) 2-6 μs 2-6 μs (1), (4) (1), (4) © 2008 Microchip Technology Inc. ...
Page 83
... ADRESH (ADDRESS:1Eh) (ADFM = 0) MSB bit 7 (ADFM = 1) bit 7 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. PIC16F785/HV785 If the conversion must be aborted, the GO/DONE bit can be cleared in software. The ADRESH:ADRESL registers will not be updated with the partially complete A/D conversion ADRESH:ADRESL registers will retain the value of the previous conversion ...
Page 84
... AN4 RC6 RC3 RC2 RC1 RC0 R/W-1 R/W-1 R/W-1 ANS2 ANS1 ANS0 bit Bit is unknown R/W-1 R/W-1 R/W-1 ANS10 ANS9 ANS8 bit Bit is unknown ANS3 ANS2 ANS1 ANS0 AN3 AN2 AN1 AN0 RA4 RA2 RA1 RA0 © 2008 Microchip Technology Inc. ...
Page 85
... This bit is automatically cleared by hardware when the A/D conversion has completed A/D conversion completed/not in progress bit 0 ADON: A/D Enable bit 1 = A/D converter module is enabled 0 = A/D converter is shut-off and consumes no operating current © 2008 Microchip Technology Inc. PIC16F785/HV785 R/W-0 R/W-0 R/W-0 CHS2 ...
Page 86
... OSC 101 = F /16 OSC 110 = F /64 OSC bit 3-0 Unimplemented: Read as ‘0’ DS41249E-page 84 R/W-0 U-0 U-0 ADCS0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 87
... For next conversion step 1 or step 2 as required. The A/D conversion time per bit is defined minimum wait required before the next acquisition starts. © 2008 Microchip Technology Inc. PIC16F785/HV785 EXAMPLE 12-1: ;This code block configures the A/D ;for polling, Vdd reference, R/C clock ;and RA0 input. ...
Page 88
... 2047 ) ln(1/2047) Rss + Rs Ω Ω 10k ln(0.0004885 0.05µs/° 50°C- 25°C ) has no effect on the equation, since it cancels itself out not discharged after each conversion. HOLD the minimum acquisition time, Ω 5. Temperature Coefficient © 2008 Microchip Technology Inc. ...
Page 89
... ANx PIN Legend Input Capacitance PIN V = Threshold Voltage Leakage current at the pin due to various junctions LEAKAGE R = Interconnect Resistance Sampling Switch C = Sample/Hold Capacitance (from DAC) HOLD © 2008 Microchip Technology Inc. PIC16F785/HV785 V DD Sampling Switch V = 0.6V T ≤ LEAKAGE V = 0.6V T ± 500 HOLD ...
Page 90
... When the A/D clock source is something other than RC, a SLEEP instruction causes the present conversion to be aborted and the A/D module is turned off. The RC ADON bit remains set. Full-Scale Range 1 LSb ideal Full-Scale Transition Analog Input Voltage 1 LSb ideal V Zero-Scale REF Transition © 2008 Microchip Technology Inc. ...
Page 91
... TRISC6 TRISC5 Legend unknown unchanged, – = unimplemented read as ‘0’. Shaded cells are not used for A/D module. © 2008 Microchip Technology Inc. PIC16F785/HV785 The appropriate analog input channel must be selected and the minimum acquisition done before the “special event trigger” sets the GO/DONE bit (starts a conversion) ...
Page 92
... PIC16F785/HV785 NOTES: DS41249E-page 90 © 2008 Microchip Technology Inc. ...
Page 93
... Phase granularity is a function of the period count value. For example, if PER<4:0> each output can be shifted in 90° steps (see Equation 13-2). © 2008 Microchip Technology Inc. PIC16F785/HV785 EQUATION 13-2: Phase 13.3 ...
Page 94
... RA2/AN2/T0CKI/INT/C1OUT pin). IH PH1EN PH2EN PWMASE SHUTDOWN PASEN pwm_clk Phase Res Counter 5 PER<4:0> pwm_count 5 PWMPH1<4:0> SHUTDOWN PH1EN 5 PWMPH2<4:0> SHUTDOWN PH2EN MASTER RB7/SYNC 5 PWMPH1<POL> S pha1 Q (1) R RC1/AN5/C12IN1-/PH1 PWMPH2<POL> S pha2 Q (1) R RC4/C2OUT/PH2 © 2008 Microchip Technology Inc. ...
Page 95
... The PH1 pin is driven by the PWM signal 0 = The PH1 pin is not used for PWM functions Note 1: Blanking is disabled when operating in complementary mode. See COMOD<1:0> bits in the PWMCON1 register (Register 13-5) for more information. © 2008 Microchip Technology Inc. PIC16F785/HV785 R/W-0 R/W-0 ...
Page 96
... Period = 31/pwm_clk 11111 = Period = 32/pwm_clk DS41249E-page 94 R/W-0 R/W-0 R/W-0 PER4 PER3 PER2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ÷ 1 ÷ 2 ÷ 4 ÷ 8 R/W-0 R/W-0 PER1 PER0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 97
... Complementary drive start is delayed by 1 pwm_clk pulse ••••• = • • • 11111 = Complementary drive start is delayed by 31 pwm_clk pulses Note 1: See PWMCON1 register (Register 13-5). © 2008 Microchip Technology Inc. PIC16F785/HV785 R/W-0 R/W-0 R/W-0 ...
Page 98
... When COMOD<1:0> PH<4:0> has no effect. Note 1: See PWMCON1 register (Register 13-5). DS41249E-page 96 R/W-0 R/W-0 R/W-0 PH4 PH3 PH2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) (1) (1) (1) (1) (1) R/W-0 R/W-0 PH1 PH0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 99
... SYNC Phase1 setup: PH<4:0> = 0x00, C1EN = 1, BLANK1 = 0 pha1 SHUTDOWN pwm_clk 2 pwm_count 0 1 Phase2 setup: PH<4:0> = 0x02, C2EN = 1, BLANK2 = 1 pha2 FIGURE 13-3: TWO-PHASE PWM START-UP TIMING F OSC PWMP<1:0> 01, PER<4:0> pwm_clk pwm_count SYNC PHnEN pwm_clk pwm_count PHnEN © 2008 Microchip Technology Inc. PIC16F785/HV785 ...
Page 100
... PWM drive pulses into Q1. If the output voltage is too high, then the voltage to the non-inverting input of Comparator 1 will fall, resulting in shorter PWM drive pulses into Q1. PIC16F785 F OSC FET Driver PH1 T -Phase WO PWM © 2008 Microchip Technology Inc. V UNREG ...
Page 101
... B'10101100' ;C1V MOVWF VRCON ;see data sheet page 72 ;Everything is setup at this point so now it is time to enable PH1 BANKSEL PWMCON0 BSF PWMCON0,PH1EN ;enable PH1 ;Module is running autonomously at this point © 2008 Microchip Technology Inc. PIC16F785/HV785 on, low range REN REF DD , -:AN6 REF DS41249E-page 99 ...
Page 102
... During shutdown the PH1 and PH2 complementary outputs are forced to their inactive states (see Figure 13-5). When shutdown ceases the PWM out- puts revert to their start-up states for the first cycle which is PH1 inactive (output undriven) and PH2 active (output driven). values of © 2008 Microchip Technology Inc. ...
Page 103
... COMPLEMENTARY OUTPUT PWM BLOCK DIAGRAM PS<1:0> F OSC Prescale 5 PWMPH1<4:0> 5 PWMPH2<4:0> PWMPH1<C1EN> C1OUT PWMPH1<C2EN> C2OUT COMOD<1:0> Note 1: Reset dominant. © 2008 Microchip Technology Inc. PIC16F785/HV785 R/W-0 R/W-0 CMDLY4 CMDLY3 CMDLY2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) PH1EN pwm_reset PH2EN PWMASE Shutdown PASEN pwm_clk ...
Page 104
... PER0 0000 0000 0000 0000 PH1EN 0000 0000 0000 0000 CMDLY0 -000 0000 -000 0000 PH0 0000 0000 0000 0000 PH0 0000 0000 0000 0000 — --00 000- --00 000- VR0 000- 0000 000- 0000 © 2008 Microchip Technology Inc. ...
Page 105
... Value at POR ‘1’ = Bit is set bit 7 EEADR: Specifies one of 256 locations for EEPROM Read/Write Operation bits © 2008 Microchip Technology Inc. PIC16F785/HV785 The EEPROM data memory allows byte read and write. A byte write automatically erases the location and writes the new data (erase before write). The EEPROM data memory is rated for high erase/write cycles ...
Page 106
... EEPROM write sequence. Note: The EECON1, EEDAT and EEADR registers should not be modified during a data EEPROM write (WR bit = 1). U-0 R/W-x R/W-0 — WRERR WREN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2008 Microchip Technology Inc. R/S-0 R/S bit Bit is unknown ...
Page 107
... WREN bit clear at all times, except when updating the EEPROM. The WREN bit is not cleared by hardware. © 2008 Microchip Technology Inc. PIC16F785/HV785 After a write sequence has been initiated, clearing the WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set ...
Page 108
... TMR2IF Value on Value on all Bit 0 POR, BOR other Resets EEADR0 0000 0000 0000 0000 RD ---- x000 ---- q000 ---- ---- ---- ---- EEDAT0 0000 0000 0000 0000 RAIF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 TMR1IF 0000 0000 0000 0000 © 2008 Microchip Technology Inc. ...
Page 109
... The INTOSC option saves system cost, while the LP crystal option saves power. A set of configuration bits are used to select various options (see Register 15.2). © 2008 Microchip Technology Inc. PIC16F785/HV785 15.1 Configuration Bits The configuration bits can be programmed (read as ‘ ...
Page 110
... R/P-0 R/P-0 — FCMEN IESO R/P-1 R/P-1 R/P-1 PWRTE WDTE FOSC2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (5) (1) (2), (3) (4) DD (5) R/P-1 R/P-1 BOREN1 BOREN0 bit 8 R/P-1 R/P-1 FOSC1 FOSC0 bit Bit is unknown (5) (5) (5) © 2008 Microchip Technology Inc. ...
Page 111
... Ripple Counter LFINTOSC Note 1: Refer to the Configuration Word register (Register 15.2). © 2008 Microchip Technology Inc. PIC16F785/HV785 They are not affected by a WDT wake-up since this is viewed as the resumption of normal operation. TO and PD bits are set or cleared differently in different Reset situations, as indicated in Table 15-2. These bits are used in software to determine the nature of the Reset ...
Page 112
... A config- for details (Section 19.0 for greater than parameter BOR slew rate. A Reset DD falls below V for less than DD BOR ). rises above DD while the Power-up Timer is BOR DD , the Power-up Timer will execute a BOR © 2008 Microchip Technology Inc. ...
Page 113
... Programming (DS41237) for more information. FIGURE 15-3: BROWN-OUT SITUATIONS V DD Internal Reset V DD Internal Reset V DD Internal Reset Note delay only if PWRTE bit is programmed to ‘0’. © 2008 Microchip Technology Inc. PIC16F785/HV785 Specification” (2000h- Specification” ( < BOR V BOR V BOR ...
Page 114
... Bit 3 Bit 2 Bit 1 SBOREN — — POR may have DD Wake-up from Sleep PWRTE = 1 1024•T 1024•T OSC OSC — — Value on Value on all Bit 0 POR, BOR other Resets BOR ---1 --qq ---1 --qq C 0001 1xxx 0001 1xxx © 2008 Microchip Technology Inc. ...
Page 115
... V DD MCLR Internal POR PWRT Time-out OST Time-out Internal Reset FIGURE 15-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH MCLR Internal POR PWRT Time-out OST Time-out Internal Reset © 2008 Microchip Technology Inc. PIC16F785/HV785 T PWRT T OST T PWRT T OST ) DD T PWRT T OST DS41249E-page 113 ...
Page 116
... Microchip Technology Inc. ...
Page 117
... If Reset was due to brown-out, then bit All other Resets will cause bit Analog channels read 0 but data latches are unknown. 7: Analog channels read 0 but data latches are unchanged. © 2008 Microchip Technology Inc. PIC16F785/HV785 Wake-up from Sleep through interrupt MCLR Reset Wake-up from Sleep through WDT Time-out ...
Page 118
... DS41249E-page 116 Program STATUS Counter Register 000h 0001 1xxx 000h 000u uuuu 000h 0001 0uuu 000h 0000 uuuu uuu0 0uuu 000h 0001 1uuu ( uuu1 0uuu © 2008 Microchip Technology Inc. PCON Register ---1 --0x ---u --uu ---u --uu ---u --uu ---u --uu ---1 --u0 ---u --uu ...
Page 119
... The GIE is cleared to disable any further interrupt • The return address is PUSHed onto the stack • The PC is loaded with 0004h © 2008 Microchip Technology Inc. PIC16F785/HV785 For external interrupt events, such as the INT pin or PORTA change interrupt, the interrupt latency will be three or four instruction cycles ...
Page 120
... Since the system clock is suspended during Sleep, only those peripherals which do not depend upon the system clock will wake the part from Sleep. See Section 15.6.1 “Wake-up from Sleep”. (1) Wake-up (If in Sleep mode) Interrupt to CPU © 2008 Microchip Technology Inc. ...
Page 121
... INTCON GIE PEIE T0IE PIE1 EEIE ADIE CCP1IE PIR1 EEIF ADIF CCP1IF Legend unknown unchanged, – = unimplemented read as ‘0’ value depends upon condition. Shaded cells are not used by the Interrupt module. © 2008 Microchip Technology Inc. PIC16F785/HV785 (1) (2) Interrupt Latency Inst ( — ...
Page 122
... STATUS_TEMP register : :(ISR) ;Insert user code here : SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W ;(sets bank to original state) MOVWF STATUS ;Move W into Status register SWAPF W_TEMP,F ;Swap W_TEMP SWAPF W_TEMP,W ;Swap W_TEMP into W DS41249E-page 120 © 2008 Microchip Technology Inc. ...
Page 123
... WDTE = 0 CLRWDT command OSC FAIL detected Exit Sleep + System Clock = T1OSC, EXTRC, INTRC, EXTCLK Exit Sleep + System Clock = XT, HS, LP © 2008 Microchip Technology Inc. PIC16F785/HV785 15.5.2 WDT CONTROL The WDTE bit is located in the Configuration Word. When set, the WDT runs continuously. ...
Page 124
... Bit 1 T0SE PSA PS2 PS1 WDTPS3 WDTPS2 WSTPS1 WDTPS0 R/W-0 R/W-0 (1) WDTPS0 SWDTEN bit Bit is unknown Value on all Value on Bit 0 other POR, BOR Resets PS0 1111 1111 1111 1111 C 0001 1xxx 000q quuu SWDTEN ---0 1000 ---0 1000 © 2008 Microchip Technology Inc. ...
Page 125
... Interrupt-on-change • External Interrupt from INT pin Other peripherals cannot generate interrupts since, during Sleep, no on-chip clocks are present. © 2008 Microchip Technology Inc. PIC16F785/HV785 When the SLEEP instruction is being executed, the next instruction ( pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit (and PEIE bit where applicable) must be set (enabled) ...
Page 126
... Memory Programming Speci- fication” (DS41237). A typical In-Circuit Serial Programming connection is shown in Figure 15-11. 0004h 0005h Inst(0004h) Inst(0005h) Dummy cycle Inst(0004h See the “PIC16F785/ IL IHH Programming Specification” © 2008 Microchip Technology Inc. ...
Page 127
... ICDCLK, ICDDATA Stack 1 level Data RAM 65h-70h, F0h Program Memory Address 0h must be NOP 700h-7FFh © 2008 Microchip Technology Inc. PIC16F785/HV785 For more information, see “MPLAB Debugger User’s Guide” (DS51331), available on Microchip’s web site (www.microchip.com). FIGURE 15-12: 28-Pin PDIP SHNTREG ...
Page 128
... PIC16F785/HV785 16.0 VOLTAGE REGULATOR The PIC16HV785 includes a permanent internal 5 volt (nominal) shunt regulator in parallel with the V This eliminates the need for an external voltage regula- tor in systems sourced by an unregulated supply. All external devices connected directly to the V share the regulated supply voltage and contribute to ...
Page 129
... The register is read, the data is modified, and the result is stored according to either the instruc- tion, or the destination designator ‘d’. A read operation is always performed, even if the instruction is a Write command. © 2008 Microchip Technology Inc. PIC16F785/HV785 For example, a CLRF instruction will read PORTA PORTA, clear all the data bits, then write the result back to PORTA ...
Page 130
... TO,PD 0000 0110 0100 1kkk kkkk kkkk Z 1000 kkkk kkkk 00xx kkkk kkkk 0000 0000 1001 01xx kkkk kkkk 0000 0000 1000 TO,PD 0000 0110 0011 C,DC,Z 110x kkkk kkkk Z 1010 kkkk kkkk © 2008 Microchip Technology Inc. ...
Page 131
... Operation: Status Affected: Z Description: The contents of W register are AND’ed with the eight-bit literal ‘k’. The result is placed in the W register. © 2008 Microchip Technology Inc. PIC16F785/HV785 ANDWF AND W with f Syntax: [label] ANDWF f,d 0 ≤ f ≤ 127 Operands: d ∈ ...
Page 132
... Clear Watchdog Timer Syntax: [ label ] CLRWDT Operands: None 00h → WDT Operation: 0 → WDT prescaler, 1 → → PD Status Affected: TO, PD Description: CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set. © 2008 Microchip Technology Inc. ...
Page 133
... If the result is ‘1’, the next instruc- tion is executed. If the result is ‘0’, then a NOP is executed instead, making it a two-cycle instruction. © 2008 Microchip Technology Inc. PIC16F785/HV785 GOTO Unconditional Branch Syntax: [ label ] GOTO k 0 ≤ ...
Page 134
... W register. The “don’t cares” will assemble as 0’s . Move label ] MOVWF f 0 ≤ f ≤ 127 (W) → (f) None 00 0000 1fff ffff Move data from W register to register ‘f’. No Operation [ label ] NOP None No operation None 00 0000 0xx0 0000 No operation. © 2008 Microchip Technology Inc. ...
Page 135
... Operation: Status Affected: None Description: Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. © 2008 Microchip Technology Inc. PIC16F785/HV785 RLF Syntax: Operands: Operation: Status Affected: Encoding: 0000 1001 ...
Page 136
... Exclusive OR Literal with W [label] XORLW k 0 ≤ k ≤ 255 (W) .XOR. k → ( 1010 kkkk kkkk The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register. © 2008 Microchip Technology Inc. ...
Page 137
... Description: Exclusive OR the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’ the result is stored back in register ‘f’. © 2008 Microchip Technology Inc. PIC16F785/HV785 f,d dfff ffff DS41249E-page 135 ...
Page 138
... PIC16F785/HV785 NOTES: DS41249E-page 136 © 2008 Microchip Technology Inc. ...
Page 139
... PICSTART Plus Development Programmer - MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2008 Microchip Technology Inc. PIC16F785/HV785 18.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market ...
Page 140
... MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. ® DSCs on an instruction © 2008 Microchip Technology Inc. ...
Page 141
... Microchip Technology Inc. PIC16F785/HV785 18.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD ...
Page 142
... K L security ICs, CAN ® IrDA , PowerSmart battery management, SEEVAL evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. © 2008 Microchip Technology Inc. ® ...
Page 143
... Exposure to maximum rating conditions for extended periods may affect device reliability. Note: Voltage spikes below V SS Thus, a series resistor of 50-100 pulling this pin directly to V © 2008 Microchip Technology Inc. PIC16F785/HV785 ................................................................................. -0. )...................................................................................................................... ± )................................................................................................................ ± – ...
Page 144
... Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Frequency denotes system clock frequency. When using the HFINTOSC the system clock is after the postscaler. 3: The internal shunt regulator of the PIC16HV785 keeps V DS41249E-page 142 ( (2) Frequency (MHz below 5.0V (nominal). ...
Page 145
... V/ms See Section 15.2.1 “Power-On Reset” for details. — 2.1 — V can be lowered in Sleep mode without losing RAM data. for PIC16HV785 device (see Table 19-14). SHUNT ≤ +85°C for industrial A ≤ +125°C for extended A Conditions ≤ 4 MHz: ≤ 10 MHz OSC ≤ ...
Page 146
... MHz OSC EC Oscillator mode MHz OSC EC Oscillator mode kHz OSC INTRC mode MHz OSC INTOSC mode MHz OSC EXTRC mode MHz OSC HS Oscillator mode or I current from this limit. Max When A/D is off, it will not consume DD © 2008 Microchip Technology Inc. ...
Page 147
... The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to V any current other than leakage current. the power-down current spec includes any such leakage from the A/D module. © 2008 Microchip Technology Inc. PIC16F785/HV785 (1), (2) Standard Operating Conditions (unless otherwise stated) Operating temperature -40° ...
Page 148
... MHz OSC EC Oscillator mode MHz OSC EC Oscillator mode kHz OSC INTRC mode MHz OSC INTOSC mode MHz OSC EXTRC mode MHz OSC HS Oscillator mode or I current from this limit. Max When A/D is off, it will not DD © 2008 Microchip Technology Inc. ...
Page 149
... Sleep mode, with all I/O pins in high-impedance state and tied to V consume any current other than leakage current. The power-down current spec includes any such leakage from the A/D module. © 2008 Microchip Technology Inc. PIC16F785/HV785 (1), (2) Standard Operating Conditions (unless otherwise stated) -40° ...
Page 150
... PIN DD μA ≤ V ≤ PIN DD μA ≤ V ≤ PIN DD μA ≤ V ≤ XT, HS and SS PIN DD LP osc configuration 8 1.6 mA 4.5V (Ind 1.2 mA 4.5V (Ext -3 -1.3 mA 4.5V (Ind -1.0 mA 4.5V (Ext RB6 pin © 2008 Microchip Technology Inc. ...
Page 151
... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 4: See Section 14.4.1 “Using the Data EEPROM” on page 105. © 2008 Microchip Technology Inc. PIC16F785/HV785 Standard Operating Conditions (unless otherwise stated) Operating temperature-40°C ≤ T ≤ ...
Page 152
... Fall H High I Invalid (High-impedance) L Low FIGURE 19-2: LOAD CONDITIONS Load Condition 1 Pin Legend 464Ω for all pins for OSC2 output DS41249E-page 150 T Time osc OSC1 SCK T0CKI t1 T1CKI Period R Rise V Valid Z High-impedance Load Condition Pin © 2008 Microchip Technology Inc. ...
Page 153
... All devices are tested to operate at ‘min’ values with an external clock applied to OSC1 pin. When an external clock input is used, the ‘max’ cycle time limit is ‘DC’ (no clock) for all devices. © 2008 Microchip Technology Inc. PIC16F785/HV785 Q1 ...
Page 154
... T — CY OSC New Value Max Units Conditions 200 ns (Note 1) 200 ns (Note 1) 100 ns (Note 1) 100 ns (Note (Note 1) — ns (Note 1) — ns (Note 1) 150 * ns 300 ns — ns — — ns — © 2008 Microchip Technology Inc. ...
Page 155
... POWER-UP TIMER TIMING V DD MCLR Internal POR 33 PWRT Time-out 32 OSC Time-out Internal Reset Watchdog Timer Reset I/O Pins © 2008 Microchip Technology Inc. PIC16F785/HV785 Freq. Min Typ† Max Tolerance ±1% 7.92 8.00 8.08 (1) ±2% 7.84 8.00 8.16 ±5% 7.60 8.00 8.40 — ...
Page 156
... T — — T OSC OSC 28* 64 132 μs — — 2.0 2.025 — 2.175 V μs 100* — — © 2008 Microchip Technology Inc. (1) Conditions = 5.0V, -40°C to +85°C = 5.0V, -40°C to +85°C = OSC1 period = 5.0V, -40°C to +85°C ≤ V (D005) BOR ...
Page 157
... Delay from external clock edge to timer increment TMR * These parameters are characterized but not tested. † Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. © 2008 Microchip Technology Inc. PIC16F785/HV785 ...
Page 158
... DS41249E-page 156 Min Typ† Max Units No Prescaler 0. With Prescaler 20 No Prescaler 0. With Prescaler — — Conditions — — ns — — ns — — ns — — ns — — prescale value (1 © 2008 Microchip Technology Inc. ...
Page 159
... Voltage Reference Output Buffer Specifications Param Symbol Characteristics No. VB01* CL External capacitor load * These parameters are characterized but not tested. © 2008 Microchip Technology Inc. PIC16F785/HV785 Standard Operating Conditions (unless otherwise stated) -40°C ≤ T Operating temperature Min Typ Max Units ±5 ±10 — ...
Page 160
... V/μs Standard Operating Conditions (unless otherwise stated) -40°C ≤ T Operating temperature A Min Typ Max Units 205 231 275 ns F maximum delay, Complementary mode © 2008 Microchip Technology Inc 50pF ≤ +125°C Comments /2, Freq load Standard load (20 kΩ ...
Page 161
... TABLE 19-14: SHUNT REGULATOR SPECIFICATIONS (PIC16HV785 only) SHUNT REGULATOR CHARACTERISTICS Param Symbol Characteristics No. SR01 V Shunt Voltage SHUNT SR02 I Shunt Current SHUNT SR03* T Settling Time SETTLE SR04* C Load Capacitance LOAD ΔI SR05* Regulator operating current SNT * These parameters are characterized but not tested. ...
Page 162
... LSb (i.e., 4 4.096V) from the last sampled voltage (as stored HOLD If the A/D clock source is selected as RC, a time added before the CY A/D clock starts. This allows the SLEEP instruction to be executed. © 2008 Microchip Technology Inc. ...
Page 163
... Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRES register may be read on the following T 2: See Table 12-1 for minimum conditions. © 2008 Microchip Technology Inc. PIC16F785/HV785 ( 131 ...
Page 164
... PIC16F785/HV785 NOTES: DS41249E-page 162 © 2008 Microchip Technology Inc. ...
Page 165
... Typical: Statistical Mean @25°C 3.0 Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 2.5 2.0 1.5 1.0 0.5 0.0 1 MHz 2 MHz 4 MHz © 2008 Microchip Technology Inc. PIC16F785/HV785 vs. F OVER V (EC MODE) OSC DD 6 MHz 8 MHz 10 MHz 12 MHz 14 MHz F OSC DD 5 ...
Page 166
... OVER V (EC MODE) OSC DD 6 MHz 8 MHz 10 MHz 12 MHz F OSC vs. F OVER V (HS MODE) OSC DD HS Mode 4.0V 3.5V 3.0V 10 MHz 16 MHz F OSC 5.5V 5.0V 4.0V 3.0V 2.0V 14 MHz 16 MHz 18 MHz 20 MHz 5.5V 5.0V 4.5V 20 MHz © 2008 Microchip Technology Inc. ...
Page 167
... Typical: Statistical Mean @25°C 800 Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 700 600 500 400 300 200 100 0 2.0 2.5 © 2008 Microchip Technology Inc. PIC16F785/HV785 vs. F OVER V (HS MODE) OSC DD HS Mode 4.0V 3.5V 3.0V 10 MHz 16 MHz F OSC vs ...
Page 168
... Max Maximum 2 2.5 2.0 23 2.5 30 DS41249E-page 166 vs. V OVER F (XT MODE) DD OSC 4 MHz 1 MHz 3.0 3.5 4.0 V (V) DD Maximum Typical 3 3 (V) DD 4.5 5.0 5.5 4.5 5 5.5 © 2008 Microchip Technology Inc. ...
Page 169
... MAXIMUM I DD 1,400 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ 1,200 (-40°C to 125°C) 1,000 800 600 400 200 0 2.0 2.5 © 2008 Microchip Technology Inc. PIC16F785/HV785 vs. V OVER F (EXTRC MODE) DD OSC 4 MHz 1 MHz 3.0 3.5 4.0 V (V) DD vs. V ...
Page 170
... DS41249E-page 168 (LFINTOSC MODE, 31 kHz) OSC LFINTOSC Mode, 31KHZ Maximum Typical 3.0 3.5 4.0 V (V) DD vs. F OVER V (HFINTOSC MODE) OSC DD 500 kHz 1 MHz 2 MHz F OSC 4.5 5.0 5.5 5.5V 5.0V 4.0V 3.0V 2.0V 4 MHz 8 MHz © 2008 Microchip Technology Inc. ...
Page 171
... Microchip Technology Inc. PIC16F785/HV785 vs. F OVER V (HFINTOSC MODE) OSC DD 500 kHz 1 MHz 2 MHz F OSC vs. V (SLEEP MODE, ALL PERIPHERALS DISABLED (Sleep Mode all Periphreals Disabled) Max 85× ...
Page 172
... Max 125°C Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) Max 85°C 3.0 3.5 4.0 V (V) DD vs. V (BOTH COMPARATORS ENABLED Max Typical 3.0 3.5 4.0 4.5 V (V) DD 4.5 5.0 5.5 5.0 5.5 © 2008 Microchip Technology Inc. ...
Page 173
... BOR I vs 160 Typical: Statistical Mean @25°C 140 Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 120 100 2.5 3.0 © 2008 Microchip Technology Inc. PIC16F785/HV785 vs. V (BOTH COMPARATORS ENABLED) CXSP Max Typical 3.5 4.0 4.5 V (V) DD OVER TEMPERATURE DD Maximum Typical 3 ...
Page 174
... DS41249E-page 172 vs. V OVER TEMPERATURE PD DD 4.5 4.75 5 6.25 7.5 8.75 10 3.0 3.5 4.0 4.5 ( vs. V OVER TEMPERATURE PD DD Max. 125°C Max. 85°C 3.0 3.5 4.0 4.5 V (V) DD 5.0 5.5 5.0 5.5 © 2008 Microchip Technology Inc. ...
Page 175
... Typical: Statistical Mean @25°C 160 Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 140 120 100 2.0 2.5 © 2008 Microchip Technology Inc. PIC16F785/HV785 OVER TEMPERATURE (HIGH RANGE) DD High Range Max. 125°C Max. 85°C Typical 3.0 3.5 4.0 V (V) DD OVER TEMPERATURE (LOW RANGE) DD Max. 125° ...
Page 176
... Min. -40°C 0.3336 0.401 0.3609 0.4354 6.5 7.0 7.5 8.0 0.3884 0.4695 I (mA) OL 0.4166 0.5049 0.4453 0.5413 0 4744 0 5782 5.0 5.5 Max. 125°C Max. 85°C 0.1503 0.1622 8.5 9.0 9.5 10.0 0.1743 0.1862 0.1984 0 2107 © 2008 Microchip Technology Inc. ...
Page 177
... Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ 1.0 (-40°C to 125°C) 0.5 0.0 0.0 -0.5 -1.0 © 2008 Microchip Technology Inc. PIC16F785/HV785 = 5.0V) DD Max. 125°C Max. 85°C Typ. 25°C Min. -40°C 6.5 7.0 7.5 8.0 8 ...
Page 178
... I (mA) OH vs. V OVER TEMPERATURE IN DD (TTL Input, -40×C TO 125×C) Max. -40°C Typ. 25°C Min. 125°C 3.0 3.5 4.0 4.5 V (V) DD Max. -40°C Typ. 25°C Min. 125°C -4.0 -4.5 -5.0 5.0 5.5 © 2008 Microchip Technology Inc. ...
Page 179
... FIGURE 20-29: LFINTOSC FREQUENCY vs. V 45,000 40,000 35,000 30,000 25,000 20,000 15,000 10,000 5,000 0 2.0 2.5 © 2008 Microchip Technology Inc. PIC16F785/HV785 vs (ST Input, -40×C TO 125×C) 3.0 3.5 4.0 V (V) DD OVER TEMPERATURE (31 kHz) DD LFINTOSC 31Khz Max. -40°C Typ. 25°C Min. 85° ...
Page 180
... Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 3.0 3.5 4.0 4.5 V (V) DD OVER TEMPERATURE DD Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 3.5 4.0 V (V) DD 5.0 5.5 4.5 5.0 5.5 © 2008 Microchip Technology Inc. ...
Page 181
... Microchip Technology Inc. PIC16F785/HV785 OVER TEMPERATURE DD -40C to +85C Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 3.5 4.0 4.5 V (V) DD OVER TEMPERATURE DD -40C to +85C Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ ...
Page 182
... FIGURE 20-34: TYPICAL HFINTOSC FREQUENCY CHANGE vs 2.0 2.5 FIGURE 20-35: TYPICAL HFINTOSC FREQUENCY CHANGE OVER DEVICE 2.0 2.5 DS41249E-page 180 3.0 3.5 4.0 4.5 V (V) DD 3.0 3.5 4.0 V (V) DD (25°C) DD 5.0 5.5 (85°C) DD 4.5 5.0 5.5 © 2008 Microchip Technology Inc. ...
Page 183
... FIGURE 20-36: TYPICAL HFINTOSC FREQUENCY CHANGE vs 2.0 2.5 FIGURE 20-37: TYPICAL HFINTOSC FREQUENCY CHANGE vs 2.0 2.5 © 2008 Microchip Technology Inc. PIC16F785/HV785 3.0 3.5 4.0 4.5 V (V) DD 3.0 3.5 4.0 4.5 V (V) DD (125°C) DD 5.0 5.5 (-40°C) DD 5.0 5.5 DS41249E-page 181 ...
Page 184
... TYPICAL VP6 REFERENCE VOLTAGE OVER TEMPERATURE (5V) Typical VP6 Reference Voltage vs. Temperature (VDD=5V) 0.66 0.64 0.62 0.6 0.58 0.56 0.54 0.52 -40 °C DS41249E-page 182 Max. Typical Min. 25°C 85°C Temperature (°C) Max. Typical Min. 25 °C 85 °C Temperature (°C) 125°C 125 °C © 2008 Microchip Technology Inc. ...
Page 185
... FIGURE 20-40: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (5V, 25°C) 100 FIGURE 20-41: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (5V, 85°C) Typical VP6 Reference Voltage Distribution (VDD=3V, 85× © 2008 Microchip Technology Inc. PIC16F785/HV785 Parts = 150 Voltage (V) Parts = 150 Voltage (V) DS41249E-page 183 ...
Page 186
... PIC16F785/HV785 FIGURE 20-42: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (5V, 125° FIGURE 20-43: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (5V, -40° DS41249E-page 184 Parts = 150 Voltage (V) Parts = 150 Voltage (V) © 2008 Microchip Technology Inc. ...
Page 187
... TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (3V, 25°C) Typical VP6 Reference Voltage Distribution (VDD=5V, 25× FIGURE 20-45: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (3V, 85°C) Typical VP6 Reference Voltage Distribution (VDD=5V, 85× © 2008 Microchip Technology Inc. PIC16F785/HV785 Parts = 150 Voltage (V) Parts = 150 Voltage (V) DS41249E-page 185 ...
Page 188
... PIC16F785/HV785 FIGURE 20-46: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (3V, 125°C) Typical VP6 Reference Voltage Distribution (VDD=5V, 25× FIGURE 20-47: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (3V, -40° DS41249E-page 186 Parts = 150 Voltage (V) Voltage (V) © 2008 Microchip Technology Inc. Parts = 150 ...
Page 189
... Microchip part number, year code, week code, and traceability code. For PIC device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. © 2008 Microchip Technology Inc. PIC16F785/HV785 Example ...
Page 190
... PIC16F785/HV785 N NOTE DS41249E-page 188 © 2008 Microchip Technology Inc. ...
Page 191
... N NOTE © 2008 Microchip Technology Inc. PIC16F785/HV785 α h φ β DS41249E-page 189 ...
Page 192
... PIC16F785/HV785 D N NOTE DS41249E-page 190 © 2008 Microchip Technology Inc. φ L ...
Page 193
... D TOP VIEW A3 © 2008 Microchip Technology Inc. PIC16F785/HV785 EXPOSED PAD NOTE 1 BOTTOM VIEW DS41249E-page 191 ...
Page 194
... PIC16F785/HV785 DS41249E-page 192 © 2008 Microchip Technology Inc. ...
Page 195
... Setup Example; Added Voltage Regulator secton. Revision D Revised VROUT min./max. limits in Table 19-9. Revision E Adding Characterization Data and small updates and reformatting. © 2008 Microchip Technology Inc. PIC16F785/HV785 APPENDIX B: MIGRATING FROM OTHER PIC DEVICES This discusses some of the issues in migrating from the ® ...
Page 196
... PIC16F785/HV785 NOTES: DS41249E-page 194 © 2008 Microchip Technology Inc. ...
Page 197
... RA4 Pin....................................................................... 40 RA5 Pin....................................................................... 40 RB4 and RB5 Pins ...................................................... 43 RB6 Pin....................................................................... 43 RB7 Pin....................................................................... 43 RC0 and RC1 Pins...................................................... 43 RC0, RC6 and RC7 Pins ............................................ 46 RC1 Pin....................................................................... 46 © 2008 Microchip Technology Inc. PIC16F785/HV785 RC2 and RC3 Pins ..................................................... 47 RC4 Pin ...................................................................... 47 RC5 Pin ...................................................................... 48 Resonator Operation .................................................. 25 Timer1 ........................................................................ 51 Timer2 ........................................................................ 56 TMR0/WDT Prescaler ...
Page 198
... Comparator................................................................. 69 Context Saving ......................................................... 120 Data EEPROM Memory Write .................................. 104 Interrupt-on-Change ................................................... 37 Oscillator Fail (OSF) ................................................... 31 PORTA Interrupt-on-change..................................... 118 RA2/INT .................................................................... 118 TMR0 ........................................................................ 118 TMR1 .......................................................................... 52 TMR2 to PR2 Match ............................................. 55, 56 INTOSC Specifications ..................................................... 153 IOCA (Interrupt-on-Change) ............................................... 37 IOCA Register..................................................................... 37 L Load Conditions................................................................ 150 © 2008 Microchip Technology Inc. ...
Page 199
... RA4 ............................................................................. 40 RA5 ............................................................................. 40 Specifications............................................................ 152 PORTB................................................................................ 42 Associated Registers .................................................. 44 Pin Descriptions and Diagrams................................... 43 RB4 ............................................................................. 43 RB5 ............................................................................. 43 RB6 ............................................................................. 43 RB7 ............................................................................. 43 PORTC ............................................................................... 45 Associated Registers ............................................ 34, 48 © 2008 Microchip Technology Inc. PIC16F785/HV785 Pin Descriptions and Diagrams .................................. 46 RC0 ............................................................................ 46 RC1 ............................................................................ 46 RC2 ............................................................................ 47 RC3 ............................................................................ 47 RC4 ............................................................................ 47 RC5 ............................................................................ 48 RC6 ............................................................................ 46 RC7 ............................................................................ 46 Specifications ........................................................... 152 Power-Down Mode (Sleep)............................................... 123 Power-up Timer (PWRT) ...
Page 200
... Control Register 1 (PWMCON1)............................... 101 Master/Slave Operation .............................................. 91 Output Blanking .......................................................... 91 Phase 1 Control (PWMPH1)....................................... 95 Phase 2 Control (PWMPH1)....................................... 96 PWM Duty Cycle......................................................... 91 PWM Frequency ......................................................... 91 PWM Period................................................................ 91 PWM Phase................................................................ 91 PWM Phase Resolution.............................................. 91 Shutdown.................................................................... 92 Two-Phase PWM Dead Time Delay ...................................................... 158 Two-Speed Clock Start-up Mode........................................ 30 © 2008 Microchip Technology Inc. ...