PIC18F248-E/SO Microchip Technology, PIC18F248-E/SO Datasheet - Page 323

• Manufacturer Part Number: PIC18F248-E/SO
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F248-E/SO

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SPI, I2C, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 4 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163011, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Data Rom Size: 256 B
• Height: 2.05 mm
• Length: 17.9 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.2 V
• Width: 7.5 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TSTFSZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
© 2006 Microchip Technology Inc.
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
No
No
No
PC
If CNT
PC
If CNT
PC
Q1
Q1
Q1
register ‘f’
operation
operation
operation
Test f, Skip if 0
[ label ]
0
a
skip if f = 0
None
If ‘f’ = 0, the next instruction fetched
during the current instruction execution
is discarded and a NOP is executed,
making this a two-cycle instruction. If ‘a’
is ‘0’, the Access Bank will be selected,
overriding the BSR value. If ‘a’ is ‘1’,
then the bank will be selected as per
the BSR value (default).
1
1(2)
Note: 3 cycles if skip and followed
HERE
NZERO
ZERO
Read
0110
No
No
No
Q2
Q2
Q2
f
=
=
=
=
[0,1]
255
by a 2-word instruction.
Address (HERE)
0x00,
Address (ZERO)
0x00,
Address (NZERO)
:
TSTFSZ f [,a]
TSTFSZ CNT
011a
:
operation
operation
operation
Process
Data
No
No
No
Q3
Q3
Q3
ffff
operation
operation
operation
operation
No
No
No
No
Q4
Q4
Q4
ffff
XORLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
W
Q1
=
=
literal ‘k’
Exclusive OR Literal with W
[ label ] XORLW k
0
(W) .XOR. k
N, Z
The contents of W are XORed with
the 8-bit literal ‘k’. The result is placed
in W.
1
1
XORLW
Read
Q2
0000
0xB5
0x1A
k
PIC18FXX8
255
0xAF
1010
Process
Data
W
Q3
DS41159E-page 321
kkkk
Write to
Q4
W
kkkk