PIC18F2480-E/ML Microchip Technology, PIC18F2480-E/ML Datasheet - Page 286

• Manufacturer Part Number: PIC18F2480-E/ML
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2480-E/ML

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SPI, I2C, MSSP, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163011, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F2480/2580/4480/4580
REGISTER 24-3:
DS39637D-page 286
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-6
bit 5
bit 4-0
Note 1:
MDSEL1
R/W-0
2:
3:
(1)
These bits can only be changed in Configuration mode. See Register 24-1 to change to Configuration mode.
This bit is used in Mode 2 only.
If FIFO is configured to contain four or less buffers, then the FIFO interrupt will trigger.
MDSEL<1:0>: Mode Select bits
00 = Legacy mode (Mode 0, default)
01 = Enhanced Legacy mode (Mode 1)
10 = Enhanced FIFO mode (Mode 2)
11 = Reserved
FIFOWM: FIFO High Water Mark bit
1 = Will cause FIFO interrupt when one receive buffer remains
0 = Will cause FIFO interrupt when four receive buffers remain
EWIN<4:0>: Enhanced Window Address bits
These bits map the group of 16 banked CAN SFRs into Access Bank addresses 0F60-0F6Dh. The
exact group of registers to map is determined by the binary value of these bits.
Mode 0:
Unimplemented: Read as ‘0’
Mode 1, 2:
00000 = Acceptance Filters 0, 1, 2 and BRGCON2, 3
00001 = Acceptance Filters 3, 4, 5 and BRGCON1, CIOCON
00010 = Acceptance Filter Masks, Error and Interrupt Control
00011 = Transmit Buffer 0
00100 = Transmit Buffer 1
00101 = Transmit Buffer 2
00110 = Acceptance Filters 6, 7, 8
00111 = Acceptance Filters 9, 10, 11
01000 = Acceptance Filters 12, 13, 14
01001 = Acceptance Filters 15
01010-01110 = Reserved
01111 = RXINT0, RXINT1
10000 = Receive Buffer 0
10001 = Receive Buffer 1
10010 = TX/RX Buffer 0
10011 = TX/RX Buffer 1
10100 = TX/RX Buffer 2
10101 = TX/RX Buffer 3
10110 = TX/RX Buffer 4
10111 = TX/RX Buffer 5
11000-11111 = Reserved
MDSEL0
R/W-0
ECANCON: ENHANCED CAN CONTROL REGISTER
(1)
W = Writable bit
‘1’ = Bit is set
FIFOWM
R/W-0
(2)
EWIN4
(1)
R/W-1
(2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
EWIN3
R/W-0
EWIN2
R/W-0
(3)
© 2009 Microchip Technology Inc.
x = Bit is unknown
EWIN1
R/W-0
EWIN0
R/W-0
bit 0