PIC18F4585-E/ML Microchip Technology, PIC18F4585-E/ML Datasheet - Page 23

• Manufacturer Part Number: PIC18F4585-E/ML
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,44PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4585-E/ML

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-QFN
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.25 KB
• Interface Type: I2C, SPI, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 44
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11 bit
• Height: 0.88 mm
• Length: 8 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.2 V
• Width: 8 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3-DB18F4680 - BOARD DAUGHTER ICEPIC3
• Lead Free Status / Rohs Status: Details

3.5
The code sequence detailed in
used, except that the address used in “Step 2” will be in
the range of 000000h to 0007FFh.
TABLE 3-9:
FIGURE 3-8:
 2010 Microchip Technology Inc.
Step 1: Enable writes and direct access to configuration memory.
Step 2: Set Table Pointer for configuration byte to be written. Write even/odd addresses.
Note 1:
Command
0000
0000
0000
0000
0000
0000
0000
0000
1111
0000
0000
0000
1111
0000
4-Bit
Boot Block Programming
Enabling the write protection of Configuration bits (WRTC = 0 in CONFIG6H) will prevent further writing of the
Configuration bits. Always write all the Configuration bits before enabling the write protection for Configuration bits.
8E A6
8C A6
0E 30
6E F8
0E 00
6E F7
0E 00
6E F6
<MSB ignored><LSB>
00 00
0E 01
6E F6
<MSB><LSB ignored>
00 00
SET ADDRESS POINTER TO CONFIGURATION LOCATION
CONFIGURATION PROGRAMMING FLOW
Data Payload
Delay P9 and P10
Time for Write
Configuration
Load Even
Program
Address
Done
Start
LSB
Table 3-5
BSF
BSF
MOVLW 30h
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPRTH
MOVLW 00h
MOVWF TBLPTRL
Load 2 bytes and start programming.
NOP - hold PGC high for time P9 and low for time P10.
MOVLW 01h
MOVWF TBLPTRL
Load 2 bytes and start programming.
NOP - hold PGC high for time P9 and low for time P10.
should be
PIC18F2XXX/4XXX FAMILY
EECON1, EEPGD
EECON1, CFGS
3.6
Unlike code memory, the Configuration bits are
programmed a byte at a time. The Table Write, Begin
Programming 4-bit command (‘1111’) is used, but only
8 bits of the following 16-bit payload will be written. The
LSB of the payload will be written to even addresses and
the MSB will be written to odd addresses. The code
sequence to program two consecutive configuration
locations is shown in
Note:
Core Instruction
Configuration Bits Programming
Delay P9 and P10
The address must be explicitly written for
each byte programmed. The addresses
can not be incremented in this mode.
Time for Write
Configuration
Load Odd
(1)
Program
Address
Start
MSB
Done
Table
3-9.
DS39622L-page 23