PIC18LF4682-I/ML Microchip Technology, PIC18LF4682-I/ML Datasheet - Page 147
![80KB Flash, 3KB RAM, ECAN, 1024 EEPROM 44 QFN 8x8x0.9mm TUBE](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC18LF4682-I/ML
Manufacturer Part Number
PIC18LF4682-I/ML
Description
80KB Flash, 3KB RAM, ECAN, 1024 EEPROM 44 QFN 8x8x0.9mm TUBE
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PCM18XT0.pdf
(484 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18F2682-ISP.pdf
(6 pages)
4.PIC18F2682-ISP.pdf
(4 pages)
Specifications of PIC18LF4682-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
80KB (40K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.25 KB
Interface Type
EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
44
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- PCM18XT0 PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F2682-ISP PDF datasheet #3
- PIC18F2682-ISP PDF datasheet #4
- Current page: 147 of 484
- Download datasheet (9Mb)
FIGURE 10-3:
FIGURE 10-4:
TABLE 10-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
© 2009 Microchip Technology Inc.
PORTD
LATD
TRISD
PORTE
LATE
TRISE
INTCON
PIR1
PIE1
IPR1
ADCON1
CMCON
Legend:
Note 1:
Name
PORTD<7:0>
PORTD<7:0>
(1)
(1)
(1)
(1)
2:
(1)
(1)
(1)
— = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port.
These registers are available on PIC18F4682/4685 devices only.
These bits are unimplemented on PIC18F2682/2685 devices and read as ‘0’.
PSPIF
PSPIF
LATD Data Output Register
PORTD Data Direction Register
GIE/GIEH
OBF
OBF
PSPIE
PSPIP
PSPIF
WR
WR
C2OUT
IBF
IBF
RD
RD
CS
CS
Bit 7
RD7
IBF
—
—
—
(2)
(2)
(2)
PARALLEL SLAVE PORT WRITE WAVEFORMS
PARALLEL SLAVE PORT READ WAVEFORMS
Q1
Q1
PEIE/GIEL
C1OUT
ADIE
ADIP
ADIF
Bit 6
OBF
RD6
—
—
—
Q2
Q2
TMR0IE
VCFG1
C2INV
IBOV
RCIE
RCIP
RCIF
Bit 5
RD5
Q3
Q3
—
—
PIC18F2682/2685/4682/4685
Q4
Q4
PSPMODE
VCFG0
INT0IE
C1INV
Bit 4
TXIF
TXIE
TXIP
RD4
—
—
Q1
Q1
PCFG3
Q2
Q2
SSPIF
SSPIE
SSPIP
RBIE
Bit 3
RD3
RE3
CIS
—
—
Q3
Q3
LATE Data Output Register
TMR0IF
CCP1IE
CCP1IP
TRISE2
CCP1IF
PCFG2
Bit 2
RD2
CM2
RE2
Q4
Q4
TMR2IF
TMR2IE
TMR2IP
TRISE1
PCFG1
Q1
Q1
INT0IF
Bit 1
RD1
CM1
RE1
Q2
Q2
TMR1IF
TMR1IE
TMR1IP
TRISE0
PCFG0
DS39761C-page 147
Bit 0
RBIF
CM0
RD0
RE0
Q3
Q3
on page
Values
Q4
Q4
Reset
54
54
54
54
54
54
51
54
54
54
52
53
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