PIC18LF4682-I/ML Microchip Technology, PIC18LF4682-I/ML Datasheet - Page 42
![80KB Flash, 3KB RAM, ECAN, 1024 EEPROM 44 QFN 8x8x0.9mm TUBE](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC18LF4682-I/ML
Manufacturer Part Number
PIC18LF4682-I/ML
Description
80KB Flash, 3KB RAM, ECAN, 1024 EEPROM 44 QFN 8x8x0.9mm TUBE
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PCM18XT0.pdf
(484 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18F2682-ISP.pdf
(6 pages)
4.PIC18F2682-ISP.pdf
(4 pages)
Specifications of PIC18LF4682-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
80KB (40K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.25 KB
Interface Type
EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
44
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- PCM18XT0 PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F2682-ISP PDF datasheet #3
- PIC18F2682-ISP PDF datasheet #4
- Current page: 42 of 484
- Download datasheet (9Mb)
PIC18F2682/2685/4682/4685
3.5.4
Certain exits from power-managed modes do not
invoke the OST at all. There are two cases:
• PRI_IDLE mode where the primary clock source
• The primary clock source is not any of the LP, XT,
TABLE 3-2:
DS39761C-page 42
Note 1:
is not stopped
HS or HSPLL modes
Primary Device Clock
T1OSC or INTRC
2:
3:
4:
5:
(PRI_IDLE mode)
Before Wake-up
Clock Source
(Sleep mode)
INTOSC
In this instance, refers specifically to the 31 kHz INTRC clock source.
T
with any other required delays (see Section 3.4 “Idle Modes”).
Includes both the INTOSC 8 MHz source and postscaler derived frequencies.
T
also designated as T
Execution continues during T
EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
CSD
OST
None
(parameter 38) is a required delay when waking from Sleep and all Idle modes and runs concurrently
is the Oscillator Start-up Timer (parameter 32). t
EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
(3)
(1)
PLL
.
IOBST
After Wake-up
Clock Source
LP, XT, HS
INTOSC
LP, XT, HS
INTOSC
LP, XT, HS
INTOSC
LP, XT, HS
INTOSC
INTRC
INTRC
INTRC
INTRC
EC, RC
EC, RC
EC, RC
EC, RC
HSPLL
HSPLL
HSPLL
HSPLL
(parameter 39), the INTOSC stabilization period.
(1)
(1)
(1)
(1)
(3)
(3)
(3)
(3)
In these instances, the primary clock source either
does not require an oscillator start-up delay, since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (RC, EC and INTIO
Oscillator modes). However, a fixed delay of interval
T
leaving the Sleep and Idle modes to allow the CPU to
prepare for execution. Instruction execution resumes
on the first clock cycle following this delay.
CSD
rc
is the PLL Lock-out Timer (parameter F12); it is
following the wake event is still required when
T
T
T
Exit Delay
OST
OST
OST
T
T
T
T
T
T
T
T
T
IOBST
IOBST
None
CSD
CSD
CSD
CSD
OST
OST
OST
+ t
+ t
+ t
(2)
(4)
(2)
(4)
(2)
(4)
(2)
rc
(5)
rc
rc
(5)
(4)
(4)
(4)
© 2009 Microchip Technology Inc.
Clock Ready Status
Bit (OSCCON)
OSTS
OSTS
OSTS
OSTS
IOFS
IOFS
IOFS
IOFS
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—
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