PIC24FJ64GA006T-I/PT Microchip Technology, PIC24FJ64GA006T-I/PT Datasheet - Page 2

• Manufacturer Part Number: PIC24FJ64GA006T-I/PT
• Description: Microcontroller
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ64GA006T-I/PT

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (22K x 24)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240011, DV164033, MA240013, AC164127, DM240001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM240011 - KIT STARTER MPLAB FOR PIC24F MCUDV164033 - KIT START EXPLORER 16 MPLAB ICD2MA160011 - DAUGHTER BOARD PICDEM LCD 16F91XDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC24FJ128GA010 FAMILY
TABLE 2:
DS80471A-page 2
Core
I
UART
Resets
Timers
SPI
JTAG
A/D
I
UART
SPI
CPU
PMP
PMP
RTCC
RTCC
I
I
UART
UART
UART
UART
UART
UART
UART
Interrupts
Output
Compare
A/D
SPI
Note 1:
2
2
2
2
C™
C
C
C
Module
Only those issues indicated in the last column apply to the current silicon revision.
Enhanced
mode
Programming
Master mode
Master mode
Slave mode
HW Flow
Control
Auto-Baud
Traps
INT0 Trigger
Framed
modes
SILICON ISSUE SUMMARY
Feature
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Number
Item
10.
12.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
11.
13
7.
1.
2.
3.
4.
5.
6.
8.
9.
SFR write issues in Doze mode.
Failure to lock out writes to I2CxTRN.
FSCM clock switch issue.
Special Event Trigger failure (Timer2/3).
Enhanced Buffer modes unavailable.
JTAG device programming not compatible
with third party solutions.
High gain error.
Failure to detect bus collision in Stop or
Restart sequences.
Erroneous FIFO buffer overflow flag.
rates.
Skipped DISI instruction under certain
circumstances.
PMRD signal absent in Master mode under
certain conditions.
Address increment/decrement failure on
back-to-back reads in Master mode.
Missed increments on simultaneous
register update.
Calibration not applied at every interval.
Failure to Acknowledge write operation in
Slave mode.
Receive mode can be enabled outside of
Idle state.
Change in Sync Break timing.
Reception failures in High-Speed mode.
UTXISEL0 bit always reads as ‘0’.
UTXSEL mode ‘10’ behaves as mode ‘00’.
Hardware flow control unavailable for some
devices and some UARTs.
Erroneous baud rate calculations in
High-Speed mode.
reception.
Failure to exit Doze mode on certain traps.
Single glitch on initialization under certain
conditions.
INT0 trigger is selected.
Frame Sync unavailable in Master mode
under certain conditions.
Parity failure with odd values in BRG.
Master mode reception errors at fast bit
Insertion of spurious data with auto-baud
Device may not wake when convert on
Issue Summary
A2
© 2009 Microchip Technology Inc.
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X
X
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X
X
X
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X
X
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X
X
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X
Affected Revisions
A3
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
C1
(1)
C2