S29GL032A10TFIR40 Spansion Inc., S29GL032A10TFIR40 Datasheet - Page 22

• Manufacturer Part Number: S29GL032A10TFIR40
• Description: Flash - NOR IC
• Manufacturer: Spansion Inc.

Specifications of S29GL032A10TFIR40

• Memory Size: 32Mbit
• Memory Configuration: 64K X 8
• Ic Interface Type: Parallel
• Access Time: 100ns
• Memory Case Style: TSOP
• No. Of Pins: 48
• Operating Temperature Range: -40°C To +85°C
• Page/burst Read Access: 25ns

Word/Byte Configuration
20
Requirements for Reading Array Data
Writing Commands/Command Sequences
The BYTE# pin controls whether the device data I/O pins operate in the byte or
word configuration. If the BYTE# pin is set at logic ‘1’, the device is in word con-
figuration, DQ0–DQ15 are active and controlled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only
data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/
O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the
LSB (A-1) address function.
To read array data from the outputs, the system must drive the CE# and OE#
pins to V
control and gates array data to the output pins. WE# should remain at V
The internal state machine is set for reading array data upon device power-up,
or after a hardware reset. This ensures that no spurious alteration of the memory
content occurs during the power transition. No command is necessary in this
mode to obtain array data. Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid data on the device data
outputs. The device remains enabled for read access until the command register
contents are altered.
See “Reading Array Data” for more information. Refer to the AC Read-Only Op-
erations table for timing specifications and the timing diagram. Refer to the DC
Characteristics table for the active current specification on reading array data.
Page Mode Read
The device is capable of fast page mode read and is compatible with the page
mode Mask ROM read operation. This mode provides faster read access speed for
random locations within a page. The page size of the device is 4 words/8 bytes.
The appropriate page is selected by the higher address bits A(max)–A2. Address
bits A1–A0 in word mode (A1–A-1 in byte mode) determine the specific word
within a page. This is an asynchronous operation; the microprocessor supplies
the specific word location.
The random or initial page access is equal to t
read accesses (as long as the locations specified by the microprocessor falls
within that page) is equivalent to t
for a subsequent access, the access time is t
are obtained by keeping the “read-page addresses” constant and changing the
“intra-read page” addresses.
To write a command or command sequence (which includes programming data
to the device and erasing sectors of memory), the system must drive WE# and
CE# to V
The device features an Unlock Bypass mode to facilitate faster programming.
Once the device enters the Unlock Bypass mode, only two write cycles are re-
quired to program a word, instead of four. The “Word Program Command
Sequence” section has details on programming data to the device using both
standard and Unlock Bypass command sequences.
IL
IL
. CE# is the power control and selects the device. OE# is the output
, and OE# to V
S29GLxxxA MirrorBit™ Flash Family
IH
.
A d v a n c e
PACC
. When CE# is deasserted and reasserted
ACC
I n f o r m a t i o n
ACC
or t
CE
or t
. Fast page mode accesses
CE
and subsequent page
S29GLxxxA_00_A2 January 28, 2005
IH
.