ADIS16250ACCZ Analog Devices Inc, ADIS16250ACCZ Datasheet - Page 5

• Manufacturer Part Number: ADIS16250ACCZ
• Description: IC ACCEL GYRO SPI PROG 18-LGA
• Manufacturer: Analog Devices Inc
• Series: iSensor™r

Specifications of ADIS16250ACCZ

• Range °/s: ±80°/s, ±160°/s, ±320°/s
• Sensitivity: ±0.2%
• Typical Bandwidth: 50Hz
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 18mA
• Output Type: SPI
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-LGA
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADIS16250/PCBZ - BOARD EVAL PCB ADIS16250
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

TIMING SPECIFICATIONS
T
Table 2.
Parameter
f
t
t
t
t
t
t
t
t
t
1
2
3
SCLK
DATARATE
STALL
CS
DAV
DSU
DHD
DF
DR
SFS
Guaranteed by design; not production tested.
The MSB presents an exception to this parameter. The MSB clocks out on the falling edge of CS . The rest of the DOUT bits are clocked after the falling edge of SCLK and
are governed by this specification.
This parameter may need to be expanded to allow for proper capture of the LSB. After CS goes high, the DOUT line goes into a high impedance state.
A
= −40°C to +85°C, V
DOUT
SCLK
DIN
CS
*NOT DEFINED
Description
Fast mode, SMPL_PRD ≤ 0x07 (f
Normal mode, SMPL_PRD ≥ 0x08 (f
Data rate period, fast mode, SMPL_PRD ≤ 0x07 (f
Data rate period, normal mode, SMPL_PRD ≥ 0x08 (f
Stall period, fast mode, SMPL_PRD ≤ 0x07 (f
Stall period, normal mode, SMPL_PRD ≥ 0x08 (f
Chip select to clock edge
Data output valid after SCLK falling edge
Data input setup time before SCLK rising edge
Data input hold time after SCLK rising edge
Data output fall time
Data output rise time
CS high after SCLK edge
Flash update time (power supply must be within range)
CC
t
CS
*
= 5.0 V, unless otherwise noted.
SCLK
1
MSB
CS
W/R
Figure 3. SPI Timing (Using SPI Settings Typically Identified as Phase = 1, Polarity = 1)
2
DB14
t
3
DAV
t
DSU
3
S
A5
DB13
≥ 64 Hz)
S
≤ 56.9 Hz)
Figure 2. SPI Chip Select Timing
4
t
DHD
2
A4
DB12
Rev. D | Page 5 of 20
t
DATARATE
S
≥ 64 Hz)
t
DATASTALL
S
5
S
≤ 56.9 Hz)
≥ 64 Hz)
A3
DB11
S
≤ 56.9 Hz)
6
A2
DB10
Min
0.01
0.01
32
42
9
12
48.8
24.4
48.8
5
50
D2
DB2
1
15
ADIS16250/ADIS16255
D1
DB1
Typ
5
5
16
LSB
LSB
Max
2.5
1.0
100
12.5
12.5
t
SFS
1
Unit
MHz
MHz
μs
μs
μs
μs
ns
ns
ns
ns
ns
ns
ns
ms