ISL29021IROZ-T7 Intersil, ISL29021IROZ-T7 Datasheet - Page 5

• Manufacturer Part Number: ISL29021IROZ-T7
• Description: IC SENSOR LIGHT-DGTL I2C 8ODFN
• Manufacturer: Intersil

Specifications of ISL29021IROZ-T7

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

of the interrupt. An unexpected camera flash, for example,
can be ignored by setting the persistency to 8 integration
cycles.
I
There are eight 8-bit registers available inside the ISL29021.
The two command registers define the operation of the device.
The command registers do not change until the registers are
overwritten. The two 8-bit data Read Only registers are for the
ADC output and the Timer output. The data registers contain
the ADC's latest digital output, or the number of clock cycles in
the previous integration period. The four 8-bit interrupt registers
hold 16-bit interrupt high and low thresholds.
The ISL29021’s I
wired as 1000100. When 1000100x with x as R or W is sent
after the Start condition, this device compares the first seven
bits of this byte to its address and matches.
2
IN
I
I
I
OUT
I
2
2
2
2
C Interface
I
C DATA
C SDA
C SDA
C CLK
2
C SDA OUT
I
I
2
2
I
C SDA IN
2
C CLK IN
C DATA
START
SDA DRIVEN BY MASTER
START
2
C interface slave address is internally hard-
A6 A5 A4 A3 A2 A1 A0 W A R7 R6 R5 R4 R3 R2 R1 R0 A
1
DEVICE ADDRESS
2
3
A6 A5 A4 A3 A2 A1 A0
1
4
SDA DRIVEN BY MASTER
DEVICE ADDRESS
5
2
5
6
3
7
4
W A
8
5
A
9
FIGURE 2. I
FIGURE 1. I
1
6
REGISTER ADDRESS
SDA DRIVEN BY MASTER
2
7
3
W
W
8
4
2
2
C WRITE TIMING DIAGRAM SAMPLE
A
A
A
9
C READ TIMING DIAGRAM SAMPLE
5
R7 R6 R5 R4 R3 R2 R1 R0
1
6
ISL29021
REGISTER ADDRESS
7
SDA DRIVEN BY MASTER
2
8
3
9
A
STOP START
4
Figure 1 shows a sample one-byte read. Figure 2 shows a
sample one-byte write. The I
the SCL (clock) line, while either the master or the slave can
drive the SDA (data) line. Figure 2 shows a sample write.
Every I
start condition (SDA falling while SCL remains high). The
following byte is driven by the master, and includes the slave
address and read/write bit. The receiving device is
responsible for pulling SDA low during the
acknowledgement period. Every I
the master asserting a stop condition (SDA rising while SCL
remains high).
For more information about the I
the Philips
5
SDA DRIVEN BY MASTER
6
2
A6 A5 A4 A3 A2 A1 A0 W A
1
C transaction begins with the master asserting a
7
™
2
DEVICE ADDRESS
8
I
3
2
A
C specification documents.
A
A
9
4
B7 B6 B5 B4 B3 B2 B1 B0
1
5
6
2
SDA DRIVEN BY MASTER
7
3
FUNCTIONS
8
2
4
C bus master always drives
A
A D7 D6 D5 D4 D3 D2 D1 D0
9
2
5
1
C standard, please consult
2
C transaction ends with
2
SDA DRIVEN BY ISL29021
6
3
DATA BYTE0
7
4
8
5
A
A
9
6
A
7
STOP
March 3, 2009
8
FN6732.0
9