ISL29029IROZ-T7 Intersil, ISL29029IROZ-T7 Datasheet - Page 4

• Manufacturer Part Number: ISL29029IROZ-T7
• Description: IC SENSOR LIGHT-PROXIMITY 8ODFN
• Manufacturer: Intersil

Specifications of ISL29029IROZ-T7

• Wavelength: 950nm
• Output Type: I²C™
• Package / Case: 8-WFDFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Electrical Specifications
NOTES:
10. Ability to guarantee I
11. For ALS applications under light-distorting glass, please see the section titled ALS Range 1 Considerations.
I2C Electrical Specifications
7. Nonlinearity is defined as: [(Measured Counts at 53 lux)-(Expected Counts at 53 lux)]/4095. Expected counts are calculated using an endpoint linear-
8. An LED is used in production test. The LED irradiance is calibrated to produce the same DATA count against a fluorescent light source of the same lux
9. An 850nm infrared LED is used to test PROX/IR sensitivity in an internal test mode.
PARAMETER
PARAMETER
I
PSRR
IRDR_LEAK
I
I
fit trendline from measurements at 0 lux and 90 lux.
level.
t
t
IRDR_0
IRDR_1
t
t
V
PULSE
HD:STA
HD:DAT
V
SU:STA
F
V
I
t
t
I
IRDR
V
SDA
V
f
V
V
V
HIGH
t
LOW
REF
INT
V
t
I2C
SCL
V
I2C
I2C
hys
SP
AA
C
IH
IL
OL
I
IH
IL
i
IRDR
i
IRDR Sink Current
IRDR Sink Current
IRDR Leakage Current
Acceptable Voltage Range on IRDR Pin
Net I
Voltage of R
I
Supply Voltage Range for I
SCL and SDA Input Low Voltage
SCL and SDA Input High Voltage
SDA Current Sinking Capability
INT Current Sinking Capability
(ΔI
2
Supply Voltage Range for I
SCL Clock Frequency
SCL and SDA Input Low Voltage
SCL and SDA Input High Voltage
Hysteresis of Schmitt Trigger Input
Low-level output voltage (open-drain) at 4mA sink
current
Input Leakage for each SDA, SCL pin
Pulse width of spikes that must be suppressed by
the input filter
SCL Falling Edge to SDA Output Data Valid
Capacitance for each SDA and SCL pin
Hold Time (Repeated) START Condition
LOW Period of the SCL clock
HIGH period of the SCL Clock
Set-up Time for a Repeated START Condition
Data Hold Time
C Clock Rate Range
IRDR
IRDR
)/(ΔV
IRDR
On Time Per PROX Reading
EXT
IRDR
leakage of ~1nA is limited by test hardware.
Pin
)
4
DESCRIPTION
DESCRIPTION
V
DD
2
2
C Interface
C Interface
= 3.0V, T
For SCL and SDA unless otherwise noted,
(Note 12).
A
= +25°C, R
ISL29029
After this period, the first clock pulse is
generated
Measured at the 30% of VDD crossing
EXT
PROX_DR = 0; V
PROX_DR = 1; V
PROX_EN = 0; V
Register bit PROX_DR = 0
V
V
PROX_DR = 0; V
OL
OL
= 499k
= 0.4V
= 0.4V
Ω
1% tolerance. (Continued)
CONDITION
DD
IRDR
IRDR
IRDR
= 3.63V (Note 10)
CONDITION
= 0.5V
= 0.5V
= 0.5V to 4.3V
V
DD
= 3V, T
A
= +25°C, R
0.05V
1300
1.25
600
MIN
600
600
1.7
-10
30
EXT
DD
1.25
MIN
0.5
1.7
90
3
3
= 499k
0.001
0.51
110
220
100
TYP
TYP
5
5
4
November 23, 2010
Ω
1% tolerance
MAX
3.63
0.55
400
900
MAX
3.63
0.55
130
400
0.4
10
50
10
4.3
1
FN7682.0
UNIT
mA/V
kHz
UNIT
µA
pF
ns
ns
ns
ns
ns
ns
ns
kHz
mA
mA
mA
mA
µA
V
V
V
V
V
µs
V
V
V
V
V