LSM2-T/6-D12NG-C Murata Power Solutions Inc, LSM2-T/6-D12NG-C Datasheet - Page 13
![DC/DC Converter](/photos/21/60/216028/4475549_sml.jpg)
LSM2-T/6-D12NG-C
Manufacturer Part Number
LSM2-T/6-D12NG-C
Description
DC/DC Converter
Manufacturer
Murata Power Solutions Inc
Datasheet
1.LSM2-T6-W3N-C.pdf
(17 pages)
Specifications of LSM2-T/6-D12NG-C
Dc / Dc Converter O/p Type
Variable
No. Of Outputs
1
Input Voltage
8.3V To 14V
Power Rating
30W
Output Voltage
5V
Output Current
6A
Approval Bodies
UL, CSA
Supply Voltage
12V
Dc / Dc Converter Case Style
SMD
Product
Non-Isolated / POL
Output Power
30 W
Input Voltage Range
10 V to 14 V
Number Of Outputs
1
Output Voltage (channel 1)
0.75 V to 5 V
Output Current (channel 1)
6 A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power Phasing Architectures
Observe the simplifi ed timing diagrams below. There are many possible power
phasing architectures and these are just some examples to help you analyze
your system. Each application will be different. Multiple output voltages may
require more complex timing than that shown here.
typical power output voltages. Generally the Master will be a primary power
voltage in the system which must be present fi rst or coincident with any
Slave power voltages. The Master output voltage is connected to the Slave’s
Sequence input, either by a voltage divider, divider-plus-capacitor or some
other method. Several standard sequencing architectures are prevalent. They
are concerned with three factors:
difference relationship is important for systems very concerned about possible
latchup of programmable devices or overdriving ESD diodes. Lower slew rates
avoid overcurrent shutdown during bypass cap charge-up.
different respective fi nal set point voltages. During the ramp, their voltages
are nearly identical. This avoids problems with large currents fl owing between
logic systems which are not initialized yet. Since both end voltages are differ-
ent, each converter reaches it’s setpoint voltage at a different time.
ing fi nal voltages at about the same time.
These diagrams illustrate the time and slew rate relationship between two
For most systems, the time relationship is the dominant factor. The voltage
In Figure 10, two POL’s ramp up at the same rate until they reach their
Figure 11 shows two POL’s with different slew rates in order to reach differ-
Figure 10. Coincident or Simultaneous Phasing (Identical Slew Rates)
The time relationship between the Master and Slave voltages
The voltage difference relationship between the Master and Slave
The voltage slew rate (ramp slope) of each converter’s output.
www.murata-ps.com
for two converters. Figure 12 is called “Inclusive” because the later starting
POL fi nishes inside the earlier POL. The timing in Figure 12 is more easily built
using a combined digital sequence controller and the Sequence/Track pin.
relationship staggered approximately the same at power-up and power-down.
Figures 12 and 13 show both delayed start up and delayed fi nal voltages
Figure 13 is the same strategy as Figure 12 but with an “exclusive” timing
Figure 12. Staggered or Sequential Phasing—Inclusive (Fixed Delays)
Figure 11. Proportional or Ratiometric Phasing (Identical V
Figure 13. Staggered or Sequential Phasing—Exclusive
Selectable-Output POL DC/DC Converters
25 Jun 2010
(Fixed Cascaded Delays)
Single Output, Non-Isolated
MDC_LSM2
LSM2 Series
email: sales@murata-ps.com
Series.B09Δ
OUT
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