ABCU-5700RZ Avago Technologies US Inc., ABCU-5700RZ Datasheet - Page 18

ROHS Gen2 Cuhead Module

ABCU-5700RZ

Manufacturer Part Number
ABCU-5700RZ
Description
ROHS Gen2 Cuhead Module
Manufacturer
Avago Technologies US Inc.
Datasheet

Specifications of ABCU-5700RZ

Data Rate
1.25Gbps
Applications
Ethernet
Voltage - Supply
3.3V
Connector Type
RJ45
Mounting Type
SFP
Data Rate Max
1.25Gbps
Supply Current
350mA
Supply Voltage
3.3V
Power Rating
1.1W
Peak Reflow Compatible (260 C)
No
Leaded Process Compatible
No
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Wavelength
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
516-1976

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ABCU-5700RZ
Manufacturer:
AVG
Quantity:
71
Part Number:
ABCU-5700RZ
Manufacturer:
AVAGO
Quantity:
8 000
Table 13. Register 10 (MASTER-SLAVE Status)
18
Bit
10.15
RO/LH/SC
10.14
RO
10.13
RO
10.12
RO
10.11
RO
10.10
RO
10.9:8
10.7:0
RO/SC
Name
MASTER-SLAVE
Configuration Fault
MASTER-SLAVE
Configuration Resolution
Local Receiver Status
Remote Receiver Status
Link Partner Full Duplex
Link Partner Half Duplex
N/A to SFP Module
Idle Error Count
Description
1 = MASTER-SLAVE
1 = Local PHY
MASTER
1 = Local Receiver OK
1 = Remote Receiver OK
OK
1 = Link Partner is capable
1 = Link Partner is capable
Counts errors when
receiving idle patterns.
configuration fault detected
0 = No MASTER-SLAVE
configuration fault detected
configuration resolved to
2 = Local PHY
configuration resolved to
SLAVE
0 = Local Receiver not OK
0 = Remote Receiver not
of 1000BASE-T full duplex
0 = Link Parnter is not
capable of 1000BASE-T full
duplex
of 1000BASE-T half duplex
0 = Link Parnter is not
capable of 1000BASE-T half
duplex
Hardware
Reset
0
0
0
0
0
0
00
00000000
Software
Reset
0
0
0
0
0
0
00
00000000
Details
clears on Auto-Negotiation
enable or Auto-Negotiation
complete. This bit is set if the
number of failed MASTER-SLAVE
resolutions reaches 7. This bit is
MASTER's or SLAVE's at the
9.11.
Page Received bit (6.1) is set to
1.
Page Received bit (6.1) is set to
1.
This bit is cleared each time that
this register is read. This bit
set if both PHY's are forced to
same time using bits 9.12 and
This bit is valid only when the
This bit is valid only when the
These bits do not roll-over when
they are all one's.

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