ADNS-2700 Avago Technologies US Inc., ADNS-2700 Datasheet - Page 14

• Manufacturer Part Number: ADNS-2700
• Description: USB SoC 3B Optical Sensor
• Manufacturer: Avago Technologies US Inc.

Specifications of ADNS-2700

• Supply Voltage Range Dc: 4V To 5.25V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 516-2297-5

One-Time-Programmable (OTP) Memory
The on chip OTP memory allows device configuration
flexibility to override the default setting of ADNS-2700
sensors without any external software driver. Once the OTP
operation is enabled, all OTP registers must be programmed
accordingly as the default values of un-program OTP
registers are always zero when L1_USE_OTP register
setting is not zero value. Tips: OTP write to the OTP register
can be skipped if the setting is zero value (0x00) in order
to save the OTP programming time.
OTP address space is from 0xDF to 0xE8. OTP can be pro-
grammed via USB interface using Set Vendor Test and Get
Vendor Test commands.
Figure 16. OTP Byte Write Flow Chart
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0x51: REGA_OTP_CONFIG[0]=1
0x52: REGA_OTP_ADDR[7:0]
0x53: REGA_OTP_DATA[7:0]
0x54: REGA_OTP_CTRL[0]=1
0x54: REGA_OTP_CTRL[0]
0x58: REGA_OTP_CTRLSTAT[0]
Write OTP address byte
Write OTP program bit
Write OTP enable bit
Read OTP program bit
Write OTP data byte
read otp status bit
OTP write pass
repeat = 1
bit = 0?
bit = 1?
bytes?
more
Done
Start
Yes
Yes
No
Yes
No
No
repeat = repeat + 1
repeat = 10?
OTP write fail
Bad Chip
No
OTP Byte Write Operation
OTP write operation flow chart is shown in Figure 16.
1. Set OTP Clock enable bit in OTP_CLOCK register, 0x42:
2. Set OTP enable bit in OTP_CONFIG register, 0x51: OTP_
3. Write the OTP register address byte to OTP_ADDR
4. Write the OTP data byte to OTP_DATA register, 0x53.
5. Set write enable bit in OTP_CTRL register, 0x54 to
6. Read the write enable bit status in OTP_CTRL register,
7. Read the write status bit in OTP_CTRLSTAT register,
8. If Step 6b is repeated up to 10 times, OTP write operation
OTP_CLOCK_EN = 1.
EN = 1.
register, 0x52.
enable write command to OTP: WR = 1.
0x54. If WR = 1, repeat reading the bit status until it is
clear.
0x58.
a. If WR_OK = 1, OTP write operation is completed.
b. If WR_OK = 0, repeat Step 4.
is failed and the chip is confirmed as defective unit.
Repeat Step 2 for more OTP byte write operations.