ADNS-5020 Avago Technologies US Inc., ADNS-5020 Datasheet - Page 14

• Manufacturer Part Number: ADNS-5020
• Description: Optoelectronic Miscellaneous, Other
• Manufacturer: Avago Technologies US Inc.

Specifications of ADNS-5020

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Burst Mode Operation
Burst mode is a special serial port operation mode that may be used to reduce
the serial transaction time for a motion read. The speed improvement is
achieved by continuous data clocking to or from multiple registers without
the need to specify the register address, and by not requiring the normal
delay period between data bytes.
Burst mode is activated by reading the Motion_Burst register. The ADNS-
5020 will respond with the contents of the Delta_X, Delta_Y, SQUAL,
Shutter_Upper, Shutter_Lower, Maximum_Pixel and Pixel_Sum registers
in that order. The burst transaction can be terminated anywhere in the
sequence after the Delta_X value by bringing the NCS pin high. After sending
the register address, the micro-controller must wait t
reading data. All data bits can be read with no delay between bytes by
driving SCLK at the normal rate. The data are latched into the output buffer
after the last address bit is received. After the burst transmission is complete,
the micro-controller must raise the NCS line for at least t
burst mode. The serial port is not available for use until it is reset with NCS,
even for a second burst transmission.
Avago Technologies highly recommends the usage of burst mode
operation in optical mouse sensor design applications.
SCLK
Notes on Power-up and Reset
The ADNS-5020 does not perform an internal power up self-reset; the
NRESET pin must be asserted low every time power is applied. There are two
ways to reset the chip, either assert low NRSET pin or by writing 0x5a to
register 0x3a. A full reset will thus be executed. Any register settings must
then be reloaded.
During power-up there will be a period of time after the power supply is
high but before any clocks are available. The table below shows the state of
the various pins during power-up and reset.
State of Signal Pins After VDD is Valid
Pin
NCS
SDIO
SCLK
XY_LED
14
MOTION_BURST REGISTER ADDRESS
During Reset
Ignored
Ignored
Ignored
Hi-Z
FIRST READ OPERATION
READ FIRST BYTE
Motion Burst Timing
t
After Reset
Functional
Depends on NCS
Depends on NCS
Functional
SRAD
SRAD
BEXIT
and then begin
to terminate
READ SECOND BYTE
READ THIRD BYTE
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