AD9957/PCBZ Analog Devices Inc, AD9957/PCBZ Datasheet - Page 34

• Manufacturer Part Number: AD9957/PCBZ
• Description: D/A Converter Evaluation Board
• Manufacturer: Analog Devices Inc
• Series: AgileRF™r

Specifications of AD9957/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Direct Digital Synthesizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9957
• Kit Contents: Board
• Main Purpose: Timing: DDS Modulators
• Embedded: No
• Utilized Ic / Part: AD9957
• Primary Attributes: 14-Bit DAC, 32-Bit Tuning Word Width
• Secondary Attributes: 1GHz, Graphical User Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9957
CLOCK INPUT (REF_CLK)
REFCLK OVERVIEW
The AD9957 supports a number of options for producing the
internal SYSCLK signal (that is, the DAC sample clock) via the
REF_CLK/ REF_CLK input pins. The REF_CLK input can be
driven directly from a differential or single-ended source, or it
can accept a crystal connected across the two input pins. There
is also an internal phase-locked loop (PLL) multiplier that can
be independently enabled. A block diagram of the REF_CLK
functionality is shown in Figure 47. The various input configu-
rations are controlled by means of the XTAL_SEL pin and
control bits in the CFR3 register. Figure 47 also shows how the
CFR3 control bits are associated with specific functional blocks.
The PLL enable bit is used to choose between the PLL path or
the direct input path. When the direct input path is selected, the
REF_CLK/ REF_CLK pins must be driven by an external signal
source. Input frequencies up to 2 GHz are supported. For input
frequencies greater than 1 GHz, the input divider must be
enabled for proper operation of the device.
When the PLL is enabled, a buffered clock signal is available at
the REFCLK_OUT pin. This clock signal is the same frequency
as the REF_CLK input. This is especially useful when a crystal
is connected, because it gives the user a replica of the crystal
clock for driving other external devices. The REFCLK_OUT
buffer is controlled by two bits as listed in Table 6.
REFCLK_OUT
REF_CLK
REF_CLK
94
90
91
DIVIDER RESETB
REFCLK
SELECT
LOGIC
INPUT
REFCLK INPUT
Figure 47. REF_CLK Block Diagram
<29:28>
DRV0
CFR3
CFR3<14>
2
XTAL_SEL
÷2
1
0
95
1
0
REFCLK INPUT
DIVIDER BYPASS
CFR3<15>
<21:19>
CHARGE
ENABLE
CFR3
IN
2
PUMP
I
CP
PLL_LOOP_FILTER
PLL_LOOP_FILTER
DIVIDE
CFR3
<7:1>
7
PLL
N
2
VCO SEL
SELECT
<26:24>
CFR3
3
VCO
OUT
PLL ENABLE
CFR3
<8>
1
0
SYSCLK
Rev. B | Page 34 of 64
Table 6. REFCLK_OUT Buffer Control
CFR3<29:28>
00
01
10
11
CRYSTAL DRIVEN REF_CLK
When using a crystal at the REF_CLK input, the resonant
frequency should be approximately 25 MHz. Figure 48 shows
the recommended circuit configuration.
DIRECT DRIVEN REF_CLK
When driving the REF_CLK/ REF_CLK inputs directly from a
signal source, either single-ended or differential signals can be
used. With a differential signal source, the REF_CLK/ REF_CLK
pins are driven with complementary signals and ac-coupled
with 0.1 µF capacitors. With a single-ended signal source, either a
single-ended-to-differential conversion can be employed or the
REF_CLK input can be driven single-ended directly. In either case,
0.1 µF capacitors are used to ac couple both REF_CLK/ REF_CLK
pins to avoid disturbing the internal dc bias voltage of ~1.35 V.
See Figure 49 for more details.
The REF_CLK/ REF_CLK input resistance is ~2.5 k Ω differen t ial
(~1.2 kΩ single-ended). Most signal sources have relatively low
output impedances. The REF_CLK/ REF_CLK input resistance is
relatively high; therefore, its effect on the termination impedance
is negligible and can usually be chosen to be the same as the output
impedance of the signal source. The bottom two examples in
Figure 49 assume a signal source with a 50 Ω output impedance.
Figure 48. Crystal Connection Diagram
39pF
REFCLK_OUT Buffer
Disabled
Low output current
Medium output current
High output current
39pF
XTAL
90
91
REF_CLK
REF_CLK