ADP2300-EVALZ Analog Devices Inc, ADP2300-EVALZ Datasheet - Page 16
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ADP2300-EVALZ
Manufacturer Part Number
ADP2300-EVALZ
Description
Nonsynchronous Step-Down Regulator Eval. Board
Manufacturer
Analog Devices Inc
Datasheet
1.ADP2301AUJZ-R7.pdf
(28 pages)
Specifications of ADP2300-EVALZ
Silicon Manufacturer
Analog Devices
Application Sub Type
Step Down DC/DC Converter
Kit Application Type
Power Management - Voltage Regulator
Silicon Core Number
ADP2300
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
ADP2300/ADP2301
APPLICATIONS INFORMATION
PROGRAMMING THE OUTPUT VOLTAGE
The output voltage of the ADP2300/ADP2301 is externally set by
a resistive voltage divider from the output voltage to the FB pin,
as shown in Figure 42. Suggested resistor values for the typical
output voltage setting are listed in Table 6. The equation for the
output voltage setting is
where:
V
R
R
Table 6. Suggested Values for Resistive Voltage Divider
V
1.2
1.8
2.5
3.3
5.0
FB1
FB2
OUT
OUT
Figure 42. Programming the Output Voltage Using a Resistive Voltage Divider
is the feedback resistor from V
is the feedback resistor from FB to GND.
(V)
V
is the output voltage.
OUT
=
ADP2300/
ADP2301
. 0
800
R
4.99
12.7
21.5
31.6
52.3
FB1
V
×
(kΩ), ±1%
⎛
⎜
⎜
⎝
FB
1
+
R
R
FB
FB
R
1
2
FB2
⎞
⎟
⎟
⎠
R
FB1
OUT
to FB.
R
10
10.2
10.2
10.2
10
FB2
(kΩ), ±1%
V
OUT
Rev. A | Page 16 of 28
VOLTAGE CONVERSION LIMITATIONS
There are both lower and upper output voltage limitations for a
given input voltage due to the minimum on time, the minimum
off time, and the bootstrap dropout voltage.
The lower limit of the output voltage is constrained by the finite,
controllable minimum on time, which can be as high as 135 ns for
the worst case. By considering the variation of both the switching
frequency and the input voltage, the equation for the lower limit
of the output voltage is
where:
V
f
t
V
The upper limit of the output voltage is constrained by the mini-
mum controllable off time, which can be as high as 120 ns in
the ADP2301 for the worst case. By considering the variation of
both the switching frequency and the input voltage, the equation
for the upper limit of the output voltage is
where:
V
f
V
t
In addition, the bootstrap circuit limits the minimum input
voltage for the desired output due to internal dropout voltage.
To attain stable operation at light loads and ensure proper startup
for the prebias condition, the ADP2300/ADP2301 require the
voltage difference between the input voltage and the regulated
output voltage (or between the input voltage and the prebias
voltage) to be greater than 2.1 V for the worst case. If the voltage
difference is smaller, the bootstrap circuit relies on some minimum
load current to charge the boost capacitor for startup. Figure 43
shows the typical required minimum input voltage vs. load current
for the 3.3 V output voltage.
SW(max)
SW(max)
MIN-ON
MIN-OFF
IN(max)
D
IN(min)
D
is the diode forward drop.
is the diode forward drop.
V
V
OUT
OUT
is the minimum controllable on time.
is the maximum switching frequency for the worst case.
is the maximum switching frequency for the worst case.
is the minimum input voltage.
is the minimum controllable off time.
is the maximum input voltage.
(max)
(min)
=
=
1 (
t
MIN
−
t
MIN
-
ON
-
OFF
×
f
×
SW
f
SW
(max)
(max)
×
)
(
×
V
(
IN
V
IN
(max)
(min)
+
+
V
V
D
D
)
)
−
−
V
V
D
D