IPR-SDRAM/DDR Altera, IPR-SDRAM/DDR Datasheet - Page 102

• Manufacturer Part Number: IPR-SDRAM/DDR
• Description: IP CORE Renewal Of IP-SDRAM/DDR
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

D–2
Adjust the PLL Phases
Assign Pins
Place the Fedback PLL
DDR and DDR2 SDRAM Controller Compiler User Guide
There is no automatic setup of the fedback PLL, or the resyncronization and
postamble clock phases in fedback clock DQS mode (refer to
To adjust the PLL phases, follow these steps:
1. On the Manual Timing tab, turn on Manual resynchronization control and
2. In Postamble clock setting, choose Dedicated clock.
3. Click Show Timing Estimates.
4. Balance the following setup and hold time properties on the Show Timing
You can now set up constraints and generate your custom variation.
When you compile a project, the add_constraints_for_<variation name>.tcl script
automatically assigns the DQ/DQS pins. To assign the other pins that are needed for
the DDR2 SDRAM interface on the Stratix II Memory Board 2, run the
<install directory>/lib/stratix_s2mb2_pins.tcl.
The fedback PLL needs to be driven directly from the input pin, and not routed
through the FPGA, otherwise the Quartus II software issues a warning and your
design does not meet timing.
On the Stratix II Memory Board 2 the fedback clock input pin is on the side of the
device, and the memory interface is on the top. Because the example design feeds the
DLL from the fedback PLL by default, the PLL is automatically placed on the top and
its clock input is therefore routed through the FPGA. To improve the design’s
timing, you should manually place the PLL on the side and drive the DLL input from
the system clock. If the fedback clock input pin is on the same side as the DQ pins, the
DLL may be fed from the fedback PLL.
Manual postamble control.
1
Estimates window, by adjusting the relevant parameter on the Manual Timing
tab.
a. For Stage 1 Resynchronization, adjust the resynchronization fedback clock
b. For Stage 2 Resynchronization, adjust the resynchronize captured read data in
c. For Stage 1 Postamble Control, adjust the postamble dedicated clock phase.
d. For Stage 1 Postamble Control, adjust the postamble cycle.
phase.
cycle.
The following parameters must be set in the given order.
Figure A–2 on page
© March 2009 Altera Corporation
Adjust the PLL Phases
A–6).