IPR-SDRAM/DDR Altera, IPR-SDRAM/DDR Datasheet - Page 39

• Manufacturer Part Number: IPR-SDRAM/DDR
• Description: IP CORE Renewal Of IP-SDRAM/DDR
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 3: Functional Description
OpenCore Plus Time-Out Behavior
OpenCore Plus Time-Out Behavior
© March 2009 Altera Corporation
f
IP Toolbench generates a clear-text VHDL or Verilog HDL datapath, which matches
your custom variation. If you are designing your own controller, Altera recommends
that you use this module as your datapath. IP Toolbench generates placement
constraints in the form of reusable scripts for all the critical registers in Cyclone series
and for the resynchronization registers in Stratix series. Altera recommends that you
also use these scripts so that your own DDR and DDR2 SDRAM designs have
consistent placement and the timing analysis script results apply to your design.
The datapath instantiates one or more data strobe (DQS) groups. The DQS group
module's control_wdata and control_rdata are fixed at 16 bits and data (DQ) is
fixed at 8 bits. To build datapaths larger than 16 bits, the datapath instantiates
multiple DQS group modules to increase the data bus width in increments of 16 bits
(8 bits for the DDR and DDR2 SDRAM side).
Figure 3–2
Figure 3–2. Datapath
Table 3–2
Table 3–2. Datapath Files
For more detail on the datapath, refer to
OpenCore Plus hardware evaluation can support the following two modes of
operation:
■
■
<variation name>_auk_ddr_datapath.v or .vhd
<variation name>_auk_ddr_clk_gen.v or .vhd
<variation name>_auk_ddr_dqs_group.v or .vhd
Untethered—the design runs for a limited time
Tethered—requires a connection between your board and the host computer. If
tethered mode is supported by all megafunctions in a design, the device can
operate for a longer time or indefinitely
shows the IP Toolbench-generated datapath files in your project directory.
shows the datapath.
control_wdata
control_rdata
Filename
clk
16
16
Data Path Module
Clock Output
Generator
Groups
DQS
“Datapath” on page
DDR and DDR2 SDRAM Controller Compiler User Guide
8
Datapath.
Clock output generator.
DQS groups.
dq
clk_to_sdram
clk_to_sdram_n
fedback_clock_out
3–4.
Description
3–3