RS08KA2 PROMO Freescale Semiconductor, RS08KA2 PROMO Datasheet - Page 21

• Manufacturer Part Number: RS08KA2 PROMO
• Description: DEMO KIT, SILICON BUNDLE, RS08KA2
• Manufacturer: Freescale Semiconductor

Specifications of RS08KA2 PROMO

• Kit Contents: DEMO9RS08KA2 Board, USB Cable, Quick Start Guide, User Manual, Packing List
• Svhc: No SVHC (15-Dec-2010)
• Development Tool Type: Demonstration Kit
• Kit Features: RS08KA2 Microcontroller,
• Silicon Manufacturer: Freescale
• Core Architecture: RS08
• Core Sub-architecture: RS08
• Silicon Core Number: MC9RS08
• Silicon Family Name: RS08KA
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ACMP_ISR:
KBI_ISR:
RTI_ISR:
LVD_ISR:
The above example illustrates the software priority handling technique. In the example the MCU enters
wait mode during the application idle state. RS08 CPU requires typically three bus cycles to wakeup from
wait mode, the interrupt latency is mainly due to the software execution time. Assuming a bus frequency
of 10MHz (bus period is 100ns) the corresponding latencies are summarized in
customize the software loop and minimize the interrupt latency according to the application requirement.
In many applications the interrupt period is much longer, it would be wise to put the MCU in stop mode
to minimize the power consumption, particularly in battery operated applications. Because the RS08 CPU
can only be waked up from stop by asynchronous interrupt source such as KBI, ACMP, etc., all
synchronous interrupt events checking such as MTIM can be eliminated from the interrupt servicing loop.
For MC9RS08KA2, all interrupt sources except MTIM has stop wakeup capability (refer to
MC9RS08KA2 data sheet for more details). On top of the software execution time the interrupt latency
from stop must include the MCU stop recovery time that allows the system clock and internal regulator to
wakeup from their standby mode. The stop recovery time varies among product families, it depends on the
clock module and internal regulator technology used.
Freescale Semiconductor
In the above example COP is refreshed before entering wait mode. In order
to avoid a COP reset, at least one interrupt event is expected within the COP
timeout period.
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;... <ISR coding> ...
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;... <ISR coding> ...
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;... <ISR coding> ...
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;... <ISR coding> ...
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NOTES:
1
Additional delay (typically 2 bus clock cycles) may exist to synchronize
the asynchronous interrupt source to the bus clock.
Table 1-6. Interrupt Latency based on 10MHz Bus Clock
InfLoop
InfLoop
InfLoop
InfLoop
InfLoop
Interrupt
ACMP
MTIM
LVD
KBI
RTI
Getting Started with RS08, Rev. 1
NOTE
Latency (µs)
1.3
1.8
2.3
2.8
0.8
1
1
1
1
Table
1-6. User is free to
Introduction to RS08
21