S1D13700F01A100 Epson, S1D13700F01A100 Datasheet - Page 212

• Manufacturer Part Number: S1D13700F01A100
• Description: Display Drivers LCD CONTROLLER
• Manufacturer: Epson

Specifications of S1D13700F01A100

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Package Type: TQFP
• Pin Count: 80
• Mounting: Surface Mount
• Operating Supply Voltage (min): 2.7V
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Memory Controller Module
General-Purpose Chip Select Module (GPCM)
User-Programmable Machine (UPM)
2.3 S1D13705 Host Bus Interface
S1D13705F00A APPLICATION NOTES
(X27A-G-010-01)
The General-Purpose Chip Select Module (GPCM) is used to control memory and peripheral
devices which do not require special timing or address multiplexing. In addition to the chip select
output, it can generate active-low Output Enable (OE) and Write Enable (WE) signals compatible
with most memory and x86-style peripherals. The MPC821 bus controller also provides a Read/
Write (RD/WR) signal which is compatible with most 68K peripherals.
The GPCM is controlled by the values programmed into the Base Register (BR) and Option Register
(OR) of the respective chip select. The Option Register sets the base address, the block size of the
chip select, and controls the following timing parameters:
• The ACS bit field allows the chip select assertion to be delayed with respect to the address bus
• The CSNT bit causes chip select and WE to be negated 1/2 clock cycle earlier than normal.
• The TRLX (relaxed timing) bit will insert an additional one clock delay between assertion of the
• The EHTR (Extended hold time) bit will insert an additional 1-clock delay on the first access to a
• Up to 15 wait states may be inserted, or the peripheral can terminate the bus cycle itself by assert-
• Any chip select may be programmed to assert BI (Burst Inhibit) automatically when its memory
The UPM is typically used to control memory types, such as Dynamic RAMs, which have complex
control or address multiplexing requirements. The UPM is a general purpose RAM-based pattern
generator which can control address multiplexing, wait state generation, and five general-purpose
output lines on the MPC821. Up to 64 pattern locations are available, each 32 bits wide. Separate
patterns may be programmed for normal accesses, burst accesses, refresh (timer) events, and
exception conditions. This flexibility allows almost any type of memory or peripheral device to be
accommodated by the MPC821.
In this application note, the GPCM is used instead of the UPM, since the GPCM has enough
flexibility to accommodate the S1D13705 and it is desirable to leave the UPM free to handle other
interfacing duties, such as EDO DRAM.
This section is a summary of the host bus interface mode used on the S1D13705 to interface to the
MPC821.
The S1D13705 implements a 16-bit interface to the host microprocessor which may operate in one
of several modes compatible with most of the popular embedded microprocessor families. The
interface mode used for the MPC821 is:
• Generic #1 (Chip Select, plus individual Read Enable/Write Enable for each byte).
valid, by 0, 1/4, or 1/2 clock cycle.
address bus and chip select. This accommodates memory and peripherals with long setup times.
chip select.
ing TA (Transfer Acknowledge).
space is addressed by the processor core.
2: INTERFACING TO THE MOTOROLA MPC821 MICROPROCESSOR
EPSON
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