MAX16826ATJ+C24 Maxim Integrated Products, MAX16826ATJ+C24 Datasheet - Page 11

• Manufacturer Part Number: MAX16826ATJ+C24
• Description: LED Drivers Programmable Four-St ring HB LED Driver w
• Manufacturer: Maxim Integrated Products

Specifications of MAX16826ATJ+C24

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX16826 provides additional flexibility with an
internal I
microcontroller (µC). The interface can be used to
dynamically adjust the amplitude of the LED current in
each LED string and the switch-mode regulator output
voltage. It can also be used to read the ADC drain volt-
age measurements for each string, allowing a µC to
dynamically adjust the output voltage to minimize the
power dissipation in the LED current sink FETs. The I
interface can also be used to detect faults such as LED
short or open.
The MAX16826 has six modes of operation: normal
mode, undervoltage lockout (UVLO) mode, thermal
shutdown (TSD) mode, shutdown (SHDN) mode,
standby (STBY) mode, and overvoltage protection
(OVP) mode.
The normal mode is the default state where each cur-
rent sink regulator is maintaining a constant current
through each of the LED strings. Digitized voltage feed-
back from the drains of the current sink FETs can be
used to establish a secondary control loop by using an
external µC to control the output of the switching stage
for the purpose of achieving low-power dissipation
across these FETs.
UVLO mode occurs when V
UVLO mode, each of the linear current sinks and the
switching regulator is shut down until the input voltage
exceeds the rising UVLO threshold.
TSD mode occurs when the die temperature exceeds
the internally set thermal limit (+160°C). In TSD mode,
each of the linear regulators and the switching regulator
is shut down until the die temperature cools by 20°C.
SHDN mode occurs when SYNC/EN is driven low. In
SHDN mode, all internal circuitry with the exception of
the shunt regulator is deactivated to limit current draw
to less than 50µA. SHDN mode disengages when
SYNC/EN is driven high or clocked.
STBY mode is initiated using the I
mode, each of the linear current sinks and the switching
regulator is shut down. STBY mode is also deactivated
using the I
regulator and the shunt regulator remain active. Whenever
Output-Voltage Optimization and Fault Detection
Programmable, Four-String HB LED Driver with
2
2
C serial interface to communicate with a
C interface. In STBY mode, the internal V
______________________________________________________________________________________
VCC
Modes of Operation
2
goes below 4.3V. In
C interface. In STBY
CC
2
C
the MAX16826 enters a mode that deactivates the switch-
ing regulator, the soft-start capacitor is discharged so that
soft-start occurs upon reactivation.
OVP mode occurs when the voltage at OVP is higher than
the internal reference. In OVP mode, the switching regula-
tor gate-drive output is latched off and can only be
restored by cycling enable, power, or entering standby
mode.
The MAX16826 features a current-mode controller that
is capable of operating in the frequency range of
100kHz to 1MHz. Current-mode control provides fast
response and simplifies loop compensation.
Output voltage regulation can be achieved in a two-
loop configuration. A required conventional control loop
can be set up by using the internal error amplifier with
its inverting input connected to FB. The bandwidth of
this loop is set to be as high as possible utilizing con-
ventional compensation techniques. The noninverting
input of this amplifier is connected to a reference volt-
age that is dynamically adjustable using the I
face. The optional slower secondary loop consists of
the external µC using the I
voltages at the drains of the current sink FETs and
adjusting the reference voltage for the error amplifier.
To regulate the output voltage, the error amplifier com-
pares the voltage at FB to the internal 1.25V (adjustable
down by using the I
of the error amplifier is compared to the sum of the cur-
rent-sense signal and the slope compensation ramp at
RSC to control the duty cycle at DL.
Two current-limit comparators also monitor the voltage
across the sense resistor using CS. If the primary cur-
rent-limit threshold is reached, the FET is turned off and
remains off for the reminder of the switching cycle. If
the current through the FET reaches the secondary cur-
rent limit, the switching cycle is terminated and the soft-
start capacitor is discharged. The converter then
restarts in soft-start mode preventing inductor current
runaway due to the delay of the primary cycle-by-cycle
current limit. The switching regulator controller also fea-
tures an overvoltage protection circuit that latches the
gate driver off if the voltage at OVP exceeds the inter-
nal 1.25V reference voltage.
Switching Preregulator Stage
2
C interface) reference. The output
2
C interface reading out the
2
C inter-
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