A4985SESTR-T Allegro Microsystems Inc, A4985SESTR-T Datasheet - Page 10

• Manufacturer Part Number: A4985SESTR-T
• Description: IC STEPPER MOTOR DRIVER 24QFN
• Manufacturer: Allegro Microsystems Inc

Specifications of A4985SESTR-T

• Applications: Stepper Motor Driver, 2 Phase
• Number Of Outputs: 1
• Current - Output: *
• Voltage - Load: 8 V ~ 35 V
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-WFQFN Exposed Pad
• Motor Type: Stepper
• No. Of Outputs: 2
• Output Current: 1A
• Output Voltage: 35V
• Supply Voltage Range: 3V To 5.5V
• Driver Case Style: QFN
• No. Of Pins: 24
• Operating Temperature Range: -20°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 620-1374 - Board Eval Motor Control A4985
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

A4985
Capacitor values should be Class 2 dielectric ±15% maximum,
or tolerance R, according to EIA (Electronic Industries Alliance)
specifications.
Enable Input
FET outputs. When set to a logic high, the outputs are disabled.
When set to a logic low, the internal control enables the outputs as
required. The translator inputs STEP, DIR, MS1, and MS2, as well
as the internal sequencing logic, all remain active, independent of
the ¯ E ¯ ¯ N ¯ ¯ A ¯ ¯ B ¯ ¯ L ¯ ¯ E ¯ input state.
Shutdown.
or an undervoltage (on VCP), the FET outputs of the A4985 are
disabled until the fault condition is removed. At power-on, the
UVLO (undervoltage lockout) circuit disables the FET outputs
and resets the translator to the Home state.
Sleep Mode
when the motor is not in use, this input disables much of the
internal circuitry including the output FETs, current regulator,
and charge pump. A logic low on the S ¯ ¯ L ¯ ¯ E ¯ ¯ E ¯ ¯ P ¯ pin puts the A4985
into Sleep mode. A logic high allows normal operation, as well as
start-up (at which time the A4985 drives the motor to the Home
microstep position). When emerging from Sleep mode, in order
to allow the charge pump to stabilize, provide a delay of 1 ms
before issuing a Step command.
Mixed Decay Operation.
Decay mode, depending on the step sequence, as shown in fig-
ures 8 through 11. As the trip point is reached, the A4985 initially
goes into a fast decay mode for 31.25% of the off-time. t
After that, it switches to Slow Decay mode for the remainder of
t
Synchronous Rectification
triggered by an internal fixed-off-time cycle, load current recircu-
lates according to the decay mode selected by the control logic.
This synchronous rectification feature turns on the appropriate
FETs during current decay, and effectively shorts out the body
diodes with the low FET R
significantly, and can eliminate the need for external Schottky
diodes in many applications. Synchronous rectification turns off
when the load current approaches zero (0 A), preventing reversal
of the load current.
OFF
. A timing dagram for this feature appears on the next page.
In the event of a fault, overtemperature (excess T
( ¯ S ¯ ¯ L ¯ ¯ E ¯ ¯ E ¯ ¯ P ¯ ). To minimize power consumption
( ¯ E ¯ ¯ N ¯ ¯ A ¯ ¯ B ¯ ¯ L ¯ ¯ E ¯ )
DS(ON)
.
This input turns on or off all of the
The bridge operates in Mixed
. This reduces power dissipation
. When a PWM-off cycle is
DMOS Microstepping Driver with Translator
OFF
.
J
)
Figure 4. Short-to-ground event
Figure 5. Shorted load (OUTxA → OUTxB) in
Slow decay mode
Figure 6. Shorted load (OUTxA → OUTxB) in
Mixed decay mode
And Overcurrent Protection
5 A / div.
5 A / div.
5 A / div.
Fast decay portion
(direction change)
Fixed off-time
Fixed off-time
115 Northeast Cutoff, Box 15036
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 [phone]
www.allegromicro.com
t →
t →
t →
Fault latched
10