A4984SESTR-T Allegro Microsystems Inc, A4984SESTR-T Datasheet
A4984SESTR-T
Specifications of A4984SESTR-T
Related parts for A4984SESTR-T
A4984SESTR-T Summary of contents
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DMOS Microstepping Driver with Translator Features and Benefits ▪ Low R outputs DS(ON) ▪ Automatic current decay mode detection/selection ▪ Mixed and Slow current decay modes ▪ Synchronous rectification for low power dissipation ▪ Internal UVLO ▪ Crossover-current protection ▪ ...
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... Internal synchronous rectification control circuitry is provided to improve power dissipation during PWM operation. Internal circuit protection includes: thermal shutdown with hysteresis, Selection Guide Part Number A4984SESTR-T 24-pin QFN with exposed thermal pad A4984SETTR-T 32-pin QFN with exposed thermal pad A4984SLPTR-T 24-pin TSSOP with exposed thermal pad ...
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A4984 VREG VDD Current Regulator REF DAC PWM Latch Blanking Mixed Decay STEP DIR RESET Translator Control MS1 Logic MS2 PWM Latch ENABLE Blanking Mixed Decay SLEEP DAC V REF DMOS Microstepping Driver with Translator Functional Block Diagram 0.22 F ...
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A4984 ELECTRICAL CHARACTERISTICS Characteristics Output Drivers Load Supply Voltage Range Logic Supply Voltage Range Output On Resistance Body Diode Forward Voltage Motor Supply Current Logic Supply Current Control Logic Logic Input Voltage Logic Input Current Microstep Select Logic Input Hysteresis ...
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A4984 THERMAL CHARACTERISTICS may require derating at maximum conditions Characteristic Symbol Package Thermal Resistance *In still air. Additional thermal information available on Allegro Web site. DMOS Microstepping Driver with Translator Test Conditions* ES package; estimated, on 4-layer PCB, based on ...
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A4984 STEP MSx RESET, or DIR STEP minimum, HIGH pulse width STEP minimum, LOW pulse width Setup time, input change to STEP Hold time, input change to STEP Figure 1. Logic Interface Timing Diagram Table 1. Microstep Resolution Truth Table ...
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A4984 The A4984 is a complete microstep- Device Operation. ping motor driver with a built-in translator for easy operation with minimal control lines designed to operate bipolar stepper motors in full-, half-, quarter-, and eighth-step modes. The currents ...
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A4984 Slow Mixed Decay Decay Missed Step Voltage on ROSC terminal 2 V/div. Step input 10 V/div. Figure 2. Missed steps in low-speed microstepping I 500 mA/div. LOAD Step input 10 V/div. Figure 3. Continuous stepping using automatically-selected mixed stepping ...
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A4984 (DIR). This determines the direction of rota- Direction Input tion of the motor. Changes to this input do not take effect until the next STEP rising edge. Internal PWM Current Control. trolled by a fixed off-time PWM current control ...
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A4984 Capacitor values should be Class 2 dielectric ±15% maximum, or tolerance R, according to EIA (Electronic Industries Alliance) specifications. ( ¯ E ¯ ¯ N ¯ ¯ A ¯ ¯ B ¯ ¯ L ¯ ¯ E ¯ ) ...
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A4984 V STEP 100.00 70.71 I OUT 0 –70.71 –100.00 I OUT Symbol I Figure 7. Current Decay Modes Timing Chart DMOS Microstepping Driver with Translator See Enlargement A Enlargement PEAK Characteristic t Device fixed off-time ...
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A4984 Layout. The printed circuit board should use a heavy ground- plane. For optimum electrical and thermal performance, the A4984 must be soldered directly onto the board. On the under- side of the A4984 package is an exposed pad, which ...
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A4984 C3 GND U1 C4 GND C5 ROSC C1 GND GND GND VDD DMOS Microstepping Driver with Translator And Overcurrent Protection OUT2B C6 GND OUT2A R4 R5 OUT1A GND OUT1B BULK GND CAPACITANCE C2 VBB LP package typical application and ...
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A4984 VDD VBB 8 V GND GND V BB VREG SENSE 10 V GND DMOS Microstepping Driver with Translator Pin Circuit Diagrams GND PGND GND MSx DIR V REG VREF ROSC DMOS SLEEP Parasitic GND And Overcurrent ...
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A4984 STEP 100.00 70.71 Phase 1 I OUT1A 0.00 Direction = H (%) –70.71 –100.00 100.00 70.71 Phase 2 I OUT2A 0.00 Direction = H (%) –70.71 –100.00 Figure 8. Decay Mode for Full-Step Increments STEP Phase 1 I OUT1A ...
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A4984 STEP 100.00 92.39 83.15 70.71 55.56 38.27 Phase 1 19.51 I OUT1A 0.00 Direction = H –19.51 (%) –38.27 –55.56 –70.71 –83.15 –92.39 –100.00 100.00 92.39 83.15 70.71 55.56 38.27 Phase 2 19.51 I OUT2B 0.00 Direction = H ...
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A4984 Table 2. Step Sequencing Settings Home microstep position at Step Angle 45º; DIR = H Phase 1 Full Half 1/4 1/8 Current Step Step Step Step [% I tripMax ] # # # # ...
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A4984 ES Package OUT2B 1 18 ENABLE 2 17 GND 3 16 PAD CP1 4 15 CP2 5 14 VCP 6 13 Terminal List Table Name ES CP1 4 CP2 5 DIR 17 ¯ E ¯ ¯ N ¯ ¯ ...
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A4984 ES Package, 24-Pin QFN with Exposed Thermal Pad 4.00 ±0. 25X 0.08 C +0.05 0.25 –0.07 0.50 BSC 0.45 MAX DMOS Microstepping Driver with Translator 4.00 ±0.15 C SEATING PLANE 0.75 ...
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A4984 ET Package, 32-Contact QFN with Exposed Thermal Pad 33X 0.08 C 0.25±0.10 0.50±0. DMOS Microstepping Driver with Translator 5.00 ±0. 5.00 ±0.15 C SEATING PLANE 0.90 ±0.10 C ...
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A4984 LP Package, 24-Pin TSSOP with Exposed Thermal Pad 7.80 ±0. 4.32±0.05 24X 0.10 C +0.05 0.25 0.65 –0.06 DMOS Microstepping Driver with Translator And Overcurrent Protection 4° ±4 0.15 3.00±0.05 4.40 ±0.10 6.40 ±0.20 ...
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A4984 Revision History Revision Rev. 1 Copyright ©2008-2011, Allegro MicroSystems, Inc. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec tions as may be required to ...