IR1152STRPBF International Rectifier, IR1152STRPBF Datasheet - Page 12

• Manufacturer Part Number: IR1152STRPBF
• Description: IC PFC ONE CYCLE CONTROL 8SOIC
• Manufacturer: International Rectifier

Specifications of IR1152STRPBF

• Mode: Continuous Conduction (CCM)
• Frequency - Switching: 53.8kHz ~ 73kHz
• Current - Startup: 26µA
• Voltage - Supply: 14 V ~ 17 V
• Operating Temperature: -25°C ~ 125°C
• Mounting Type: *
• Package / Case: *
• Uvlo: 10.1V
• Supply Voltage Range: 14V To 17V
• Startup Current: 26µA
• Operating Supply Current: 9mA
• Duty Cycle (%): 99%
• Frequency: 66kHz
• Digital Ic Case Style: SOIC
• No. Of Pins: 8
• Rohs Compliant: Yes
• Operating Temperature Range: -25°C To +125°C
• Peak Reflow Compatible (260 C): Yes
• Package: 8-lead SOIC
• Circuit: PFC IC
• Vcc Range (v): 14V-17V
• Out Peak Current (a): +/- 0.75
• Switching Frequency (khz): 66
• Environment: Industrial
• Over-voltage Protection: Dual OVP
• Brown-out Protection: Yes
• Pbf: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: IR1152STRPBFTR

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State & Transitions Diagram
V
BOP
V
FB
< V
OR
< V
BOP
OLP
(VTH)
Present PulseTerminated
IPK LIMIT
Oscillator Active
Gate Inactive
FAULT
V
V
CC
OVP
< V
OR
< V
CC UVLO
SLEEP
|V
|V
|V
|V
V
V
ISNS
V
ISNS
ISNS
ISNS
CC
OVP
V
V
V
CC
CC
OVP
OVP
| < |V
< V
| > |V
| > |V
| < |V
< V
OR
< V
< V
OR
OR
<V
< V
CC UVLO
CC UVLO
V
CC UVLO
SLEEP
ISNS(PK)
V
12
ISNS(PK)
ISNS(PK)
ISNS(PK)
SLEEP
OVP
SLEEP
FB
V
COMP
> V
> V
V
V
V
BOP
OVP
V
|
CC
|
OR
|
|
OVP
FB
OVP
< V
AND
> V
AND
AND
Present PulseTerminated
> V
> V
AC POWER ON
UVLO/SLEEP
Internal Circuits Biased
Internal Circuits Biased
> V
SOFT START
(VTH)
STAND – BY
(VTH)
OVP FAULT
COMP,START
Vcomp Discharged
Vcomp Discharged
CCON
SLEEP
BOP(EN)
OLP
Oscillator Active
NORMAL
Oscillator Active
Oscillator Active
Internal Circuits
Gate Inactive
Gate Inactive
Gate Inactive
Gate Inactive
V
C
Gate Active
Gate Active
MODE
MODE
Unbiased
COMP
Z
Charging
Rising
Cz fully charged
V
V
OVP
V
FB
V
V
BOP
CC
OVP
< V
< V
AND
V
< V
FB
< V
OVP(RST)
OR
< V
OVP(RST)
OR
< V
CC UVLO
V
V
BOP
BOP
BOP
SLEEP
OLP
(VTH)
V
< V
FB
< V
OR
< V
BOP
BOP
OLP
(VTH)
(VTH)
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