IR1152STRPBF International Rectifier, IR1152STRPBF Datasheet - Page 9

• Manufacturer Part Number: IR1152STRPBF
• Description: IC PFC ONE CYCLE CONTROL 8SOIC
• Manufacturer: International Rectifier

Specifications of IR1152STRPBF

• Mode: Continuous Conduction (CCM)
• Frequency - Switching: 53.8kHz ~ 73kHz
• Current - Startup: 26µA
• Voltage - Supply: 14 V ~ 17 V
• Operating Temperature: -25°C ~ 125°C
• Mounting Type: *
• Package / Case: *
• Uvlo: 10.1V
• Supply Voltage Range: 14V To 17V
• Startup Current: 26µA
• Operating Supply Current: 9mA
• Duty Cycle (%): 99%
• Frequency: 66kHz
• Digital Ic Case Style: SOIC
• No. Of Pins: 8
• Rohs Compliant: Yes
• Operating Temperature Range: -25°C To +125°C
• Peak Reflow Compatible (260 C): Yes
• Package: 8-lead SOIC
• Circuit: PFC IC
• Vcc Range (v): 14V-17V
• Out Peak Current (a): +/- 0.75
• Switching Frequency (khz): 66
• Environment: Industrial
• Over-voltage Protection: Dual OVP
• Brown-out Protection: Yes
• Pbf: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: IR1152STRPBFTR

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Programmable Soft Start
The soft start process controls the rate of rise of the
voltage feedback loop error signal thus providing a
linear increase of the RMS input current that the
PFC converter will admit. The soft start time is
essentially controlled by voltage error amplifier
compensation
therefore user programmable to some degree
based on desired voltage feedback loop crossover
frequency.
Gate Drive Capability
The gate drive output stage of the IC is a totem
pole driver with 750mA peak current drive
capability. The gate drive is internally clamped at
13V (Typ). Gate drive buffer circuits can be easily
driven with the GATE pin of the IC to suit any
system power level.
System Protection Features
IR1152 protection features include Brown-out
protection (BOP), Open-loop protection (OLP),
Overvoltage protection (OVP), Cycle-by-cycle peak
current limit (IPK LIMIT), Soft-current limit and VCC
under voltage lock-out (UVLO).
- BOP is based on direct input line sensing using a
resistor divider/RC filter network. If BOP pin falls
below the Brown-out protection threshold V
Brown-out situation is immediately detected and
the following response is executed - the gate drive
pulse is disabled, VCOMP is actively discharged
and IC is pushed into Stand-by Mode. The IC re-
enters normal operation only after BOP pin
exceeds V
Stand-by Mode until this pin exceeds V
- OLP is activated whenever the VFB pin voltage
falls below V
detected the following response is immediately
executed - the gate drive is immediately disabled,
VCOMP is actively discharged and the IC is
pushed into Stand-by mode. There is no voltage
hysteresis associated with this feature. During
start-up the IC is held in Stand-by Mode until VFB
exceeds V
IR1152 General Description
OLP
BOP(EN)
.
OLP
components
. During start-up the IC is held in
threshold. Once open loop is
selected
BOP(EN)
and
.
BOP
, a
is
9
- OVP feature in IR1152 is "dual" and "dedicated".
There are 2 overvoltage comparators in IR1152 -
marked OVP(OVP) and OVP(VFB) in the block
diagram. Both these are identical in design, reference
the exact same thresholds and thus identical in
operation. The non-inverting input of OVP(VFB)
comparator is on the VFB pin while that of the
OVP(OVP) comparator is on the OVP/EN pin. When
either or both of the pin voltages exceeds V
overvoltage situation is detected and the gate drive is
immediately terminated. The gate drive is re-enabled
only after both pin voltages are below V
redundancy offered by the 2 comparators and use of
a dedicated OVP/EN pin ensures the best possible
system overvoltage protection against extremes of
situations such as component failures, pin-to-pin
shorts etc.
- Soft-current limit is an output voltage fold-back type
protection feature encountered when the PFC
converter input current exceeds to a point where the
V
amplitude of input current is directly proportional to
V
clamped to a certain maximum voltage inside the IC
(given by V
input current causes the V
maximum value, then any further increase in input
current will cause the duty cycle to droop which
immediately forces the V
converter to fold-back. Since the highest current is at
the peak of the AC sinusoid, the droop in duty cycle
commences at the peak of the AC sinusoid when the
soft-current limit is encountered. In most converters,
the design of the current sense resistor is performed
based on soft-current limit (i.e. V
the system condition which demands highest input
current (minimum V
-
instantaneously turns-off the gate output whenever
the ISNS pin voltage exceeds V
magnitude. The gate drive is held in the low state as
long as the overcurrent condition persists. The gate
drive is re-enabled when the magnitude of ISNS pin
voltage falls below the V
protection feature incorporates a leading edge
blanking circuit to improve noise immunity.
m
m
, the error voltage of the feedback loop. V
Cycle-by-cycle
voltage saturates. As mentioned earlier, the
COMP,EFF
AC
peak
parameter in datasheet). If the
& maximum P
m
OUT
current
© 2011 International Rectifier
voltage to saturate at its
ISNS(PK)
voltage of the PFC
m
ISNS(PK)
IR1152S
saturation) and at
OUT
limit
threshold. This
).
OVP(RST)
threshold in
protection
OVP
. The
, an
m
is