CRD-42528 Cirrus Logic Inc, CRD-42528 Datasheet

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CRD-42528

Manufacturer Part Number
CRD-42528
Description
Audio Modules & Development Tools Reference Design for CS42528 + CS493XX
Manufacturer
Cirrus Logic Inc
Datasheet

Specifications of CRD-42528

Product
Audio Modules
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
http://www.cirrus.com
ANALOG
Supports 4 digital S/PDIF
(IEC60958/IEC61937) inputs
8 Discrete analog inputs using the CS42528
+ 3 external CS5351 ADCs for 8 analog
channels of input at 48 kHz and 96 kHz
2 Channel upsampling supported
8 Discrete analog outputs from the CS42528
2 Digital S/PDIF (IEC60958/IEC61937)
outputs using the CS42528 Mux and
XMT958 transmitter on the CS49300
On board SRAM for AAC 5.1 discrete
channel decoding
In system programmable Flash, capable of
holding 16 DSP programs
8 x
Preliminary Product Information
Reference Design for the CS49300 and CS42528
SBR
SBL
Sub
Rs
Ls
R
C
L
SPDIF
4 x
AIN
AIN
CS5351
CS5351
SDOUT
SDOUT
AIN
Ext ADC
RXP3
RXP0
RXP1
RXP2
AIN
CS5351
In
SDOUT
SAI
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
CDI
DAI
Copyright
CS493XX-IBA
(or CS492XX)
Description
The CRD42528 is a reference design for the CS49300
DSP family and the CS42528 CODEC. It supports up to
8 channels of analog input at 48 and 96 kHz, or
2 channels of analog input at 192 kHz. One of four
digital S/PDIF inputs may be selected. Additionally, up
to 2 channels of digital S/PDIF output and 8 channels of
analog output at up to 192 kHz are supported. The on
board SRAM is included to allow for AAC 5.1 discrete
channel decoding, and on-board flash memory is
included to allow in-system programming of up to
16 DSP images. The DSP supports the following
algorithms, including (but not limited to) AAC, Dolby
Digital (AC-3), Dolby Digital EX, DTS, DTS-ES, DTS
Neo:6, Cirrus Original Surround (including COS 6.1),
SRS CircleSurround, SRS TruSurround, Pro Logic II,
MPEG Multichannel (including EX), and HDCD.
The control interface to the CRD42528 is the UDSP
System Platform. All control and data I/O is connected
to headers, which allows the CRD42528 to be used
easily in a end system or as a reference design. A larger
block diagram is shown on the next page.
ORDERING INFORMATION
CS42528
(All Rights Reserved)
SRAM/Flash
CRD42528
External
EMAD
Cirrus Logic, Inc. 2003
AUDATA0
AUDATA1
AUDATA2
AUDATA3
Reference Design
CX_SDIN1
CX_SDIN2
CX_SDIN3
CX_SDIN4
CRD42528
AOUT1
AOUT2
AOUT3
AOUT4
AOUT5
AOUT6
AOUT7
AOUT8
DS586RD2
IEC60958
MAY’ 03
L
R
Ls
Rs
C
Sub
SBL / Lt
SBR / Rt
1

Related parts for CRD-42528

CRD-42528 Summary of contents

Page 1

... SBR Preliminary Product Information http://www.cirrus.com Description The CRD42528 is a reference design for the CS49300 DSP family and the CS42528 CODEC. It supports channels of analog input at 48 and 96 kHz channels of analog input at 192 kHz. One of four digital S/PDIF inputs may be selected. Additionally channels of digital S/PDIF output and 8 channels of analog output 192 kHz are supported ...

Page 2

... CS5351 ANALOG C SDOUT AIN Sub CS5351 SBL AIN SBR CS42528 CS493XX-IBA (or CS492XX) SAI CDI DAI EMAD SDOUT External SRAM/Flash Figure 1. Block Diagram of the CRD42528 AOUT1 AOUT2 AOUT3 AOUT4 AUDATA0 CX_SDIN1 AOUT5 AUDATA1 CX_SDIN2 AOUT6 CX_SDIN3 AUDATA2 AOUT7 CX_SDIN4 AUDATA3 AOUT8 IEC60958 L R ...

Page 3

... APPENDIX F: Bill of Materials - CRD42528 .................................................................32 APPENDIX G: UDSP Schematics ...................................................................................37 APPENDIX H: Bill of Materials - UDSP.........................................................................46 LIST OF FIGURES Figure 1. Block Diagram of the CRD42528 ..................................................................................... 2 Figure 2. Mute Control Rev A.......................................................................................................... 9 Figure 3. Mute Control - Corrected ................................................................................................. 9 Figure 4. Data and Clock Connections for 8 Channel Analog Input and Output ........................... 10 Contacting Cirrus Logic Support pro estio iries con tact a C irrus ales R e pre se ntative ...

Page 4

Figure 5. Clock and Data Connections for S/PDIF (IEC61937 / IEC60958) Input ........................ 11 Figure 6. Control and Data I/O ...................................................................................................... 16 Figure 7. DSP................................................................................................................................ 17 Figure 8. External Memory ............................................................................................................ 18 Figure 9. CoDec ............................................................................................................................ 19 Figure 10. External ...

Page 5

... QUICK START A PC with an ECP parallel port, a stereo analog audio source, and powered speakers are required to use the CRD42528 in the mode specified in this Quick Start. 1) Install the drivers supplied with the board on the PC. Refer to “UDSP Schematics” on page 37 for details on installing the drivers. ...

Page 6

... These batch files can be run from the DOS prompt like the “analog_in_96kHz.bat” file. Please note that while only license-free code is supplied with the CRD42528, a complete list of algorithms supported by the CRD42528 (including Dolby 6 Digital EX and DTS-ES) is available from your local Cirrus Logic, Inc ...

Page 7

... DAO port. This PCM data is input on the CS42528’s CX port. The CS42528 then converts the audio data back to analog. 2.2 Control Control of the CRD42528 is done via the UDSP headers (J2 and J3) in either SPI or I ferent resistors must be populated or not populated according to the desired communication mode. ...

Page 8

... R, Ls, Rs, C, Sub) 8 (L, R, Ls, Rs, C, Sub, SBL/Lz, SBR/Rz) Table 2. Analog Input Assembly Options 2.3.2 Analog Output Options The CRD42528 supports channels of an- alog output. A list of components that needs to be populated for each configuration is shown in Table 3. Number of Analog Output Channels ...

Page 9

... For a full list of codes (including IBA codes) and their requirements, please contact your local Cirrus Field Applications Engineer. 2.4 Revision A Errata The revision A CRD42528 requires the following modification to the mute circuitry. The mute signal as shown in Figure 2 should be modified as shown ...

Page 10

SBL / SBR Analog In CS5351 Sub Analog In CS5351 ADC Data 4 Channels CS42528 ADCIN AIN Analog In Analog Input / Output Figure 4. Data and Clock Connections for 8 ...

Page 11

CS42528 SAI Port RXP S/PDIF (IEC61937 / IEC60958) CX Port Analog Input / Output Figure 5. Clock and Data Connections for S/PDIF (IEC61937 / IEC60958) Input SAI Clocks(CS42528) / CDI Clocks(CS49300) at 128 Fs SCLK, LRCLK=Fs 2 Channels or Compressed ...

Page 12

... The UDSP drivers have now been successfully ® ® Windows 95 , installed. The CRD42528 kit is now ready for use. ® ) allow any Several demonstration batch files (*.bat) are available in the CRD42528\Configs directory. Please see the information on the use of these batch files. ...

Page 13

... APPENDIX B: CRD42528.INI # Horizontal Fields: # [part] [I2Caddr] [SPIaddr] [SPI CSn] # [reset(bit to drop in PLD addr 0x01)] # [INTREQ_NUM] [Print Format] #[Parallel word length] [Parallel CSn] #[Read_Type Vertical Fields: #board - first non-comment, non-blank line #parts - other lines # note: reset can only take on values 01, Default is CS4930 interface ...

Page 14

... Please note that most non-DSP The devices require an aborted write operation to properly set the MAP pointer before reading. The device list file, called CRD42528.INI, must follow a very specific format. An example of this can be found “CRD42528.INI” on page file should not be changed. ...

Page 15

URD.exe - Program used to read back responses from a target device DSP-type device is selected and the INTREQ pin is not low when URD.exe is executed, the program will wait until INTREQ drops. Press the ‘Enter’ key ...

Page 16

APPENDIX D: SCHEMATICS Figure 6. Control and Data I/O ...

Page 17

Figure 7. DSP ...

Page 18

Figure 8. External Memory ...

Page 19

Figure 9. CoDec ...

Page 20

Figure 10. External A/D Converters ...

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Figure 11. L/R Input Filters ...

Page 22

Figure 12. Ls/Rs Input Filters ...

Page 23

Figure 13. C/Sub Input Filters ...

Page 24

Figure 14. SBL/SBR Input Filters ...

Page 25

Figure 15. L/R Output Filters ...

Page 26

Figure 16. Ls/Rs Output Filters ...

Page 27

Figure 17. C/Sub Output Filters ...

Page 28

Figure 18. SBL/SBR Output Filters ...

Page 29

APPENDIX E: LAYOUT PLOTS (GROUND PLANE VIAS ARE FLOODED) Figure 19. Top Layer ...

Page 30

Figure 20. Bottom Layer ...

Page 31

Figure 21. Assembly Drawing ...

Page 32

... APPENDIX F: BILL OF MATERIALS - CRD42528 Item Qty Reference 1 20 5361A_SDAT 5361B_SDAT CX_LRCK CX_SCLK CX_SDIN1 CX_SDIN2 CX_SDIN3 CX_SDIN4 CX_SDOUT INT OMCK RMCK RST- SAI_LRCK SAI_SCLK SAI_SDOUT TP1 TP2 TP3 TP4 C34 C37 C44 C52 C54 C62 C63 C69 C71 C79 C85 C87 C103 C105 ...

Page 33

Item Qty Reference 9 1 C16 10 1 C17 11 1 C18 12 10 C20 C56 C72 C89 C111 C117 C126 C140 C147 C156 13 1 C21 14 8 C23 C88 C110 C116 C127 C139 C148 C155 15 6 C29 ...

Page 34

Item Qty Reference Q11 Q12 Q13 R27 R38 R47 R56 R65 R74 R86 R29 R31 R39 ...

Page 35

Item Qty Reference 35 9 R11 R145 R151 R152 R153 R158 R159 R162 R164 36 8 R15 R34 R43 R52 R61 R70 R82 R91 37 6 R17 R19 R20 R76 R129 R154 38 1 R21 39 1 R23 40 8 ...

Page 36

Item Qty Reference U10 U22 U23 U18 U33 51 1 U16 52 2 U19 U20 53 1 U21 54 1 U27 U24 57 ...

Page 37

APPENDIX G: UDSP SCHEMATICS +15V GND -15V +5V FOR PHIHONG PSA-46-304 SERIAL AUDIO I/O 1 SERIAL AUDIO I/O 2 Figure 22. UDSP - Top ANALOG I/O CONTROL1 POWER/CONTROL2 SPDIF I/O ...

Page 38

DAP VL SEL Figure 23. UDSP - Digital Audio Port DIGITAL AUDIO PORT ...

Page 39

Figure 24. UDSP - Headphone Amplifier + ...

Page 40

ON OFF OSC PWR RESET RUN PROG uC OFF ON JTAG I/F SPI/I2C MODE F_A[18..0] 512K X 8 FLASH DISPLAY/CONTROL HEADERS NOTES: 1. SHORTING TRACES ACROSS HEADER PINS MUST BE CUT BEFORE DEBUG HEADER INSTALATION AND USE EXTERNAL CONTROL Figure ...

Page 41

Figure 26. UDSP - Power VL SEL + + + ...

Page 42

Figure 27. UDSP - Parellel Port Interface ...

Page 43

Figure 28. UDSP - RS232 Interface (CD_O) (DSR_O) (TX) (RTS_I) (RX) (CTS_O) (DTR_I) (RI_O) ...

Page 44

Figure 29. UDSP - RS422 Interface ...

Page 45

Figure 30. UDSP - S/PDIF I/O ...

Page 46

APPENDIX H: BILL OF MATERIALS - UDSP Item Qty Reference C11 C13 C14 C15 C16 C17 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C39 C40 C42 ...

Page 47

Item Qty Reference 23 1 J32 24 1 J34 25 4 JX28 JX30 JX32 JX34 26 1 J35 27 2 J36 J47 28 1 J37 29 1 J38 30 1 J39 31 1 J40 32 2 J45 J48 33 1 ...

Page 48

Item Qty Reference R18 R19 R21 R22 R28 R31 R32 R33 R35 R36 R37 R41 R42 R43 51 20 R82 R83 R87 R88 R89 R90 52 5 R20 R52 R53 R54 R55 R23 R24 R25 R34 R39 R40 R48 53 ...

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Item Qty Reference UX5 UX9 80 2 U11 U18 81 3 U12 U13 U14 82 1 U15 83 1 U16 84 ...

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