STA013EVB STMicroelectronics, STA013EVB Datasheet - Page 29

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STA013EVB

Manufacturer Part Number
STA013EVB
Description
Audio Modules & Development Tools Eval Brd for STA013$
Manufacturer
STMicroelectronics
Datasheet

Specifications of STA013EVB

Description/function
Audio DSPs
Product
Audio Modules
For Use With/related Products
STA013x
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
5.4. TIMING DIAGRAMS
5.4.1. Audio DAC Interface
a) OCLK in output. The audio PLL is used to clock the DAC
tsdo = 3.5 + pad_timing (Cload_SDO) - pad_timing
tsckt = 4 + pad_timing (Cload_SCKT) - pad_timing
tlrckt = 3.5 + pad_timing (Cload_LRCCKT) -
b) OCLK in input.
Thi min = 3ns
Tlo min = 3ns
Toclk min = 25ns
tsdo = 5.5 + pad_timing (Cload_SDO) ns
tsckt = 6 + pad_timing (Cload_SCKT) ns
tlrckt = 5.5 + pad_timing (Cload_LRCKT) ns
(Cload_ OCLK)
(Cload_ OCLK)
pad_timing (Cload_ OCLK)
OCLK (OUTPUT)
OCLK (INPUT)
LRCLK
LRCLK
SCKT
SCKT
SDO
SDO
t
t
t
t
t
t
sckt
lrclk
sdo
sdo
sckt
lrclk
t
hi
t
oclk
t
Pad-timing versus load
Cload_XXX is the load in pF on the XXX output.
pad_timing (Cload_XXX) is the propagation delay
added to the XXX pad due to the load.
lo
Load (pF)
100
25
50
75
STA013 - STA013B - STA013T
D98AU969
D98AU970
Pad_timing
2.90ns
3.82ns
4.68ns
5.52ns
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