XAUI-PM-U1 Lattice, XAUI-PM-U1 Datasheet - Page 17

• Manufacturer Part Number: XAUI-PM-U1
• Description: Development Software XAUI 10Gb Ethernet
• Manufacturer: Lattice

Specifications of XAUI-PM-U1

• Tool Type: Development Software Support
• Core Architecture: CPLD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 9. XAUI IP Core Registers (Continued)
Table 10. XAUI Vendor Specific Registers 4.9xxxh
Input/Output Timing
XGMII Specifications
Clause 46 if IEEE 802.3ae specifies HSTL1 I/O with a 1.5V output buffer supply voltage for all XGMII signals. The
HSTL1 specifications comply with EIA/JEDEC standard EIA/JESD8-6 using Class I output buffers with output
impedance greater than 38¾ to ensure acceptable overshoot and undershoot performance in an unterminated
interconnection. The parametric values for HSTL XGII signals are given in Table 11. The HSTL termination scheme
is shown in Figure 11. Timing requirements for chip-to-chip XGMII signals are shown in Figure 12.
4.24.2
4.24.1
4.24.0
4.25.15:3
4.25.2
4.25.1:0
4.8000.[15:0]
4.8001.15
4.8002.[15:8]
4.8002.[7:0]
4.8003.[15:8]
4.8003.[7:0]
4.9xxxx.[15:8] Unused
4.9xxxx.[7:0]
Bit(s)
Bit(s)
Lane 2 Sync (not
supported)
Lane 1 Sync (not
supported)
Lane 0 Sync (not
supported)
Reserved
Receive test pattern
enable
Test pattern select
MCA Sync Request
MCA Sync Status
Unused
GPO
Unused
GPI
PCS register access Bit [7:0] are directly mapped to sci_data port.
Name
Name
Status is available from the PCS core
Status is available from the PCS core
Status is available from the PCS core
Value always 0
0 = Receive test pattern not enabled
00
Writing any value to this register triggers the MCA sync
request. This register always read as 0.
This bit provides MCA synchronization status.
Bit [15:8] are unused
This field controls the General Purpose Outputs (GPO)
when the MDIO is enabled. It is intended to control optional
ports of the PCS core.
Bit [15:8] are unused
This field senses the state of the General Purpose Inputs
(GPI) when the MDIO is enabled. It is intended to sense the
status control of the PCS core.
Bit [15:8] are unused
Address [5:0] are directly mapped to sci_address port [5:0].
Address bit [8:6] are used to decode which SCI quad is
being selected.
[8:6] = 0 SCI0 is selected
[8:6] = 1 SCI1 is selected
[8:6] = 2 SCI2 is selected
[8:6] = 3 SCI3 is selected
[8:6] = 4 SCI AUX is selected
17
Description
Description
XAUI IP Core User’s Guide
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
Reset Value
Reset Value
0 0
0 0
0 0
00
0
0
0
0
0
0
0
0
0
0